Civil Engineering Reference
In-Depth Information
8.2.2
Formulation of the optimization problem
A basic formulation.
The transistor sizing problem for a combinational
block in an edge-triggered circuit is most commonly formulated as
where is the size of the transistor (out of total transistors) in the circuit.
The objective function approximates the area of a circuit as a weighted sum
of transistor sizes‚ a metric that is correlated with the circuit area‚ but not‚ an
exact measure. An accurate metric for the area occupied by a circuit requires
consideration of the layout arrangement‚ the cell structures and the design
style. This is unlikely to yield a well-behaved functional form‚ and therefore
the above approximation is widely used since it possesses the properties of
continuity and differentiability that are desirable from the point of view of a
general nonlinear optimizer. Consequently‚ from the point of view of transistor
sizing‚ the approximate area function in the objective is considered adequate.
The constraint function for edge-triggered circuits simply states that the
delay of each combinational block should not exceed a number‚ which
depends on the clock period‚ the setup times‚ and the skew tolerances. Strictly
speaking‚ a hold time constraint should also be incorporated‚ but this is often
taken care of in the design methodology in a separate step from transistor sizing.
For level-clocked circuits‚ the delay constraints are more complex and must take
into account the possibility of multicycle paths‚ as described in Section 7.3.
In addition to Equation (8.1)‚ several other formulations may be useful.
These include
Minimizing
for some exponent
Minimizing the dynamic‚ short-circuit‚ or active/standby leakage power un-
der an area specification‚
A formulation that enumerates all constraints.
In Equation (8.1)‚ the
constraint implies that the delay on
every
combinational path in
the circuit must be less than (for an edge-triggered circuit). The number
of paths in a circuit could be exponential in the number of gates in a circuit‚
and therefore‚ any optimizer that requires these constraints to be enumerated
literally experiences great difficulty with such a formulation. For this reason‚
the formulation in (8.1) is used by optimizers such as TILOS and iCONTRAST
that do not require constraint enumeration.
For optimizers where the constraints must be explicitly listed‚ a method
suggested in [Mar86‚ MG87‚ MG86] employs intermediate variables to reduce
the number of delay constraints from exponential to linear in the circuit size.
This is achieved as follows. As in the CPM method‚ the circuit is modeled by
a graph‚
G(V‚ E)‚
where
V
is the set of nodes (corresponding to gates) in
G
‚
