Civil Engineering Reference
In-Depth Information
In other words, before the beginning of the precharge for next cycle, the correct
evaluation result must have traveled to the output node.
For example, in Figure 7.8, the rising event of the output node of domino
gate with output
o
must satisfy (7.26). Therefore,
where
are the rising event times at inputs
and
respectively
represents the delay of a falling transition at the dynamic
node due to a rising transition at input
represents the rise delay of the inverter feeding the gate output node
o
is the delay from the clock node
to the dynamic node
Therefore for
The relation (7.28) corresponds to the requirement that the rising edge of each
input should appear in time for the falling edge of the evaluate clock so as to
allow sufficient time for the output to be discharged.
The relation (7.29) ensures that the pulse width of the evaluate clock is suf-
ficient for pulling down the output node when the last transistor to switch is
the lowermost one, connected to the clock node.
(iii) The third set of constraints addresses the timing requirements on rise
transitions at the dynamic node The rising event of the domino gate must
be completed before the rising edge of the evaluation clock, i.e.,
If the rise time of the dynamic node through the
fed by the clock
is denoted by
then the rising event time can be expressed as:
This leads to the constraint given by
This implies that the pulse width of precharge must be capable of pulling up
the output node.
Note that unlike (ii) above, the delay to only node is considered here, and
not to the output node
o.
Note that the constraint to node
o
is very loose and
is satisfied except in the most pathological cases. There are two possibilities:
