TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS - Timing - page 137

the clock in a level-clocked circuit to allow combinational paths to have a delay
of more than the clock period is referred to variously as either cycle borrowing,
cycle stealing, slack stealing, or time borrowing.
For edge-triggered circuits, the insulating nature of the memory elements
leads to the requirement that the delays through all combinational logic paths
must be less than the clock period, with an allowance for setup and hold time
constraints. Therefore, timing constraints need only be enforced between FF's
connected by a purely combinational path. For level-clocked circuits, due to
cycle borrowing, the delay through a combinational logic path may be longer
than one clock cycle, as long as it is compensated by shorter path delays in
subsequent cycles.
To ensure that the extra delay is compensated, we must enforce timing
constraints between a latch and every other latch reachable from it via a path
that traverses combinational logic, and possibly multiple latches.

Example. Consider a linear N stage acyclic pipeline with N + 1 memory
elements If these memory elements were edge-triggered FF's,
then we would need only N timing constraints (from the path
). However, if these memory elements were to be level sensitive latches,
then we would need N ·( N + 1)/2 timing constraints and
to check the correctness of multicycle paths. In the presence of feedback
paths, the timing analysis of level-clocked circuits would become even more
complex.
As will soon be shown, some of this complexity can be reduced by the intro-
duction of an appropriate set of intermediate variables.

7.3.2 Clock models

Single-phase and multiphase clocking. The most conventional form of
clocking uses a single-phase clock, where every rising [falling] clock edge is
perfectly aligned with every other rising [falling] clock edge, assuming that no
skews are introduced by the clock distribution network. Some high-performance
circuits may, instead, use multiphase clocking; in a clock, the phases
typically have the same clock period, but are staggered from each other by a
fixed time delay. Each phase consists of two intervals: an active interval during
which the latches are enabled, and a passive interval when they are disabled;
these typically correspond to the interval when the clock signal is high and low,
respectively.
Depending on the way the clock scheme is designed, the phases may be
overlapping or nonoverlapping, i.e., their active times may or may not simul-
taneously intersect in time with any other phase. Clocking schemes may be
designed to be symmetric, which implies that all phases have an equal ac-
tive time, and the time difference between the rising clock edges for successive
phases and are all equal; a clock scheme that does not satisfy this property
is said to be asymmetric.