Civil Engineering Reference
In-Depth Information
7.3
CLOCKING DISCIPLINES: LEVEL-CLOCKED CIRCUITS
7.3.1
Introduction
As mentioned in Section 7.1, unlike an edge-triggered FF, a level-clocked latch
is transparent during the active period of the clock. This makes the analysis
and design of level-clocked circuits more complex than edge-triggered circuits,
since combinational blocks are not insulated from each other by the memory
elements, and multicycle paths are possible when the data is latched during the
transparent phase of the clock. Even though this transparent nature introduces
an additional level of complexity to the design phase, level-clocked circuits are
often used for high-performance designs since they offer more flexibility than
edge-triggered circuits, both in terms of the minimum clock period achievable
and the minimum number of memory elements required.
As an illustration of this notion, consider the simple circuit in Figure 7.4
with unit delay gates and a single-phase clocking scheme with a 50% duty
cycle. Let us assume that the data signals are available at the primary inputs
at the falling edge of the clock, and must arrive at the primary outputs before
the appropriate falling edge, several clock cycles later. At the level-triggered
latch L1, the data may depart at any time while the clock is high. A data
signal in this circuit is allowed precisely two clock periods to reach the primary
output from the primary input.
We will now use this example to demonstrate the advantage of using level
clocked circuits over edge-triggered circuits. For simplicity, we will assume zero
setup and hold times here. Consider the operation of the circuit under a clock
period of 2 units; notice that the path delay between latch L1 and the output
is more than the clock period. However, the circuit works correctly due to the
transparent nature of the latches. As shown in the figure, the data departs from
the IN node at time 0, arrives at and departs from the latch L1 at time 1, and
is latched at the output at time 4, which corresponds to the onset of the second
clock edge. In contrast, if L1 were an edge-triggered FF, then a clock period of
2 units would have been untenable, since the clock period would correspond to
the largest combinational block delay, which implies that the minimum possible
clock period would have been 3 units. This practice of using the active period of
