Civil Engineering Reference
In-Depth Information
the gate from the input to the output. In general‚ can be written as
a function of the process parameters
P
of the gate‚ the loading capacitance of
the driving interconnect tree and the succeeding gates that it drives
and the input signal transition time
at this input pin of the gate:
The sensitivities of the gate delay to the process parameters can be found
applying the chain rule for computing derivatives.
Since the gate delay differs at the different input pins‚ in conventional
static timing analysis‚ is set to if the path ending at the output of
the gate traversing the input pin has the longest path delay. In statistical
static timing analysis‚ each of the paths through different gate input pins has a
certain probability to be the longest path. Therefore‚
should be computed
as a weighted sum of the distributions of the gate delays
where the weight
equals the probability that the path through the
pin is the longest among
all others:
where is the distribution of path delay at the gate output through the
input pin. The calculation of and can be achieved by
the “sum” and the “max” operators‚ as discussed in Section 5.2.1. It is clearly
to see that is now approximated as a normal distribution‚ since it is as a
weighted sum of normal distributions Using the formulation above‚ the
derivatives of to the process parameters can also be computed through the
weighted sum of the derivatives of
to the process parameters.
6.3
EARLY WORK ON STATISTICAL STA
Early work by [DIY91] presented a method for performing statistical timing
analysis while including structural Boolean properties of a combinational cir-
cuit. The approach used a discrete PDF and encoded both the delay and logic
behavior of the circuit into a Boolean expression that was subsequently sim-
plified using a BDD representation. Although the results of this method were
shown on small circuits‚ a notable observation was related to the computation
of the signal probability (i.e.‚ the probability that the signal is at logic 1) at
the output of a gate.
Notationally‚ let be the probability that a line is at logic 1 at time
Temporarily assuming that each gate has zero delay‚ the line probability at
the gate output can be calculated for various gates. For example‚ if the inputs
of the gate are
and the output is
then
