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two paths‚ and these are correlated since the delays of a and d contribute to
both paths. It is important to take such structural correlations‚ which arise
due to reconvergences in the circuit‚ into account while performing SSTA.
6.2.4
Modeling gate/interconnect delay PDF's
We will now show how the variations in the process parameters are translated
into PDF's that describe the variations in the gate and interconnect delays that
correspond to the weights on the nodes and edges, respectively, of the statistical
timing graph.
In Section 6.2.1, the geometrical parameters associated with the gate and
interconnect are modeled as normally distributed random variables. Before we
introduce how the distributions of gate and interconnect delays will be modeled,
let us first consider an arbitrary function
that is assumed to be a
function on a set of parameters
P
, where each
is a random variable
with a normal distribution given by
We can approximate
linearly using a first order Taylor expansion:
where is the nominal value of calculated at the nominal values of parame-
ters in the set
P
‚ is computed at the nominal values of
is a normally distributed random variable and
If all of the parameter variations can be modeled by Gaussian distributions‚
this approximation implies that is a linear combination of Gaussians‚ which
is therefore Gaussian. Its mean
and variance
are:
where is the covariance of and
This approximation is valid when has relatively small variations‚ in
which domain the first order Taylor expansions is adequate and the approxi-
mation is acceptable with little loss of accuracy. This is generally true of the
impact of intra-chip variations on delay‚ where the process parameter variations
are relatively small in comparison with the nominal values‚ and the function
changes by a small amount under this perturbation. For this reason‚ the gate
and interconnect delays‚ as functions of the process parameters‚ can be approx-
imated as a normal distributions when the parameter variations are assumed
to be normal.
Computing the PDF of gate delay
For a multiple-input gate‚ the pin-to-
pin delay of the gate differs at different input pins. Let
be the delay of
