Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances - Complex System Modelling and Control Through Intelligent Soft Computations - page 712

Fig. 5 Proposed co-design methodology approach

automating hardware/software partitioning step (basing of the hardware/software
costs) using a high-level speci cation. Figure 5 illustrates our design methodology.

cation, proposed practically by all hardware/software par-
titioning approaches is replaced, in our approach, by a high-level speci

The low-level speci

cation. This

high-level speci ned as

nodes to make possible its integration on the hardware or software architecture.
Beginning with a high-level speci

cation is divided into functional nodes (C functions) de

cation, in the hardware/software partitioning step

permits the classi cation of nodes on software or hardware without specifying the

implementing target which allows the portability of our design process. Before
partitioning, designers have to evaluate the costs of nodes (in term of execution time
and area consumption) and the time taken for communication between software and
hardware nodes. For software nodes, these costs are computed using pro ler (e.g.

compiling c code on MicroBlaze using the directive -pg, permit the generation of the
pro

ling of each C function). However, hardware costs are measured after hardware
synthesis of the high-level speci cation using HLS approaches. As hardware/soft-

ware algorithms partitioning, we selected the Integer Linear Programing (ILP)
algorithm. Figure 6 details our approach on hardware/software partitioning.