Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 236

est GPS receivers with high analog front end design content utilized digital
processing in the receiver baseband processing, receiver control, navigation, and
user interface areas. The custom component digital technology known as ASICs,
FPGAs, DSPs, and general purpose microprocessors are advancing so rapidly that
all GPS receiver manufacturers currently use digital processing at higher levels of the
signal processing functions. Also, the processing speed along with built-in floating
point processors enables the modern GPS receiver designer to use optimum algo-
rithms rather than approximations. Fortunately, as the feature sizes of ASICs and
FPGAs become smaller, their power consumption is reduced and their speed is
increased. These advances in technology not only reduce the component count,
which reduces cost and power and increases reliability, but also can greatly improve
performance. For this reason, outdated analog GPS receiver processing techniques
were not discussed.
The partitioning between the microprocessor or DSP and the custom digital
components depends on the digital signal processing throughput capability (bit
manipulation and computational speed) of the microprocessor or DSP. Eventu-
ally DSPs may take over the role of ASICs and FPGAs. It is important to keep in
mind that every process performed in the microprocessor is performed in sequential
steps, whereas the custom digital components (ASICs or FPGAs) typically perform
their processing in parallel. However, the speed of ASICs and FPGAs has increased
to the point where digital multiplexing (time sharing of the same function) is now
used.
The digital data is sampled data, and there is real time between these samples in
which the DSP or microprocessor can process the previous data. The processor is
interrupted every time the sampled data is updated. This is called real-time process-
ing, and the real-time processor must have completed all of the tasks within the
interrupt time line and have some throughput resources left over for additional pro-
cesses that are scheduled for completion on longer time lines. Fortunately, the nature
of GPS digital signal processing is such that as the processing steps become more
complex, there is also more real time allowed between the processes to complete the
signal processing. For example, in a C/A code digital GPS receiver, the digital sam-
ples containing the spread spectrum signals at IF of all of the visible SVs must be pro-
cessed at a rate of 2 to 6 MHz (and even faster for modern wideband narrow
correlator designs). The replica C/A code generators (one per SV tracked) must oper-
ate at 1.023 MHz. At these processing speeds, it is unlikely that the speed-power
product of general purpose microprocessors will make them the suitable choice to
perform the carrier and code wipeoff functions in the very near future—perhaps
never—but specialized DSPs might eventually make a showing. However, after the
SV signals have been despread, the processing rate per SV seldom exceeds 1 kHz and
typically is of the order of 50 to 200 Hz per SV, which is well within the real-time
signal processing capability of a modern microprocessor. The navigation process in
a GPS receiver seldom exceeds 1 Hz, even for a high dynamics application.
Since extensive use is made of non-real-time computer modeling and simula-
tions for all aspects of a GPS receiver design, including external aiding, the ideal
design environment is one that permits the stripping away of test features not
required for real-time operation and the porting of the real-time programs into the
actual GPS receiver hardware without modification of the source code [23].