Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 235

phase lock indicator is not reset until several loss of phase lock comparisons are
made in a row. Typical values for the design parameters are: DT = 20 ms, K 1 =

0.0247, K 2 = 1.5, L P = 50, and L 0 = 240.

5.11.3 False Frequency Lock and False Phase Lock Detector
False frequency lock can occur in FLL. This can be detected when the DLL velocity
state does not match the FLL velocity state. Since both exist, only a comparison
check is necessary in FLL to correct the FLL velocity state.
False phase lock can occur in PLL operation when the phase lock indicator
declares phase lock but the PLL replica frequency state is incorrect. The incorrect
frequency is typically some multiple of 25 Hz for the C/A and P(Y) code signals. The
FLL-assisted PLL loop design ordinarily prevents false phase lock, but it is prudent
to implement a false phase lock indicator to detect this possible false carrier loop
condition. The false phase lock indicator is used only when the phase lock indicator
declares that a phase lock condition exists.
Figure 5.44 is a design example of a false phase lock indicator. It performs a fre-
quency discriminator function on a pair of prompt in-phase and quadraphase sam-
ples, I Pi 1 , Q Pi −1 , I Pi and Q Pi formed into the cross product, C , and dot product, D ,
functions shown as inputs into the detector. Typically, the in-phase and
quadraphase samples are collected every 10 ms and the C and D products are
formed every DT 20 ms, then applied to the input. These are integrated and

dumped for N samples (typically N

=

1 second intervals,
the four-quadrant arctangent is computed with output E . The absolute value of E
represents the change in phase in 1 second, F , which is in units of hertz; this is com-
pared to a threshold, G (for this example, this is 15.5 Hz). If D exceeds G , then the
pessimistic phase lock indicator is set to “false” and a 25-Hz correction is applied to
the carrier accumulator based on the sign of E .

= 50). Typically, at N × DT =

5.12 Use of Digital Processing

The use of digital processing was as important to the feasibility of the GPS naviga-
tion concept as the advancement of reliable space qualified atomic standards. The
computational burdens in the GPS space segment, control segment, and user seg-
ment are such that digital signal processing is an indispensable asset. Even the earli-

DT NDT

•

N
i= ∑

C

Y

False lock:
correct carrier
accumulator

YES

E F

DT NDT ATAN2(Y,X) F>G? •

N
i= ∑

D

NO

X

True lock

Figure 5.44 False phase lock detector.