Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 182

bilinear integrator shown in Figure 5.19(c). The last digital integrator is not included
because this function is implemented by the NCO. The NCO is equivalent to the
boxcar integrator of Figure 5.19(b).
Figure 5.21 illustrates two FLL-assisted PLL loop filter designs (see footnote 1).
Figure 5.21(a) depicts a second-order PLL filter with a first-order FLL assist. Figure
5.21(b) depicts a third-order PLL filter with a second-order FLL assist. If the PLL
error input is zeroed in either of these filters, the filter becomes a pure FLL. Simi-
larly, if the FLL error input is zeroed, the filter becomes a pure PLL. The lowest noise
loop closure process is to close in pure FLL, then apply the error inputs from both
discriminators as an FLL-assisted PLL until phase lock is achieved, then convert to
pure PLL until phase lock is lost. However, if the noise bandwidth parameters are
chosen correctly, there is very little loss in the ideal carrier tracking threshold perfor-
mance when both discriminators are continuously operated [7]. In general, the natu-
ral radian frequency of the FLL, ω 0 f , is different from the natural radian frequency of

the PLL, ω 0 p . These natural radian frequencies are determined from the desired loop

filter noise bandwidths, B nf and B np , respectively. The values for the second-order
coefficient a 2 and third-order coefficients a 3 and b 3 can be determined from Table
5.6. These coefficients are the same for FLL, PLL, or DLL applications if the loop
order and the noise bandwidth, B n , are the same. Note that the FLL coefficient inser-
tion point into the filter is one integrator back from the PLL and DLL insertion
points. This is because the FLL error is in units of hertz (change in range per unit of
time), whereas the PLL and DLL errors are in units of phase (range).
A loop filter parameter design example will clarify the use of the equations in
Table 5.6. Suppose that the receiver carrier tracking loop will be subjected to high

Frequency
error input

ω 0f

T

+

Phase
error input

+

+ +

ω 0 2

T T

1/2 Σ Σ Σ

+

+ +

Z − 1

.

Velocity accumulator

a 20p

ω

(a)

a 20f ω

2

T

ω 0f

Frequency
error input

+

+

+

+ +

+ + +

ω 0 3

T T S 1/2 1/2 T 1/2

Σ

Phase
error input

Σ Σ Σ Σ Σ Σ Σ

+ + + +

+ +

Z − 1 Z − 1

Acceleration
accumulator

2

a 30p ω

Velocity accumulator

b 30p

ω

(b)

Figure 5.21 Block diagrams of FLL-assisted PLL filters: (a) second-order PLL with first-order FLL
assist, and (b) third-order PLL with second-order FLL assist.