Satellite Signal Acquisition, Tracking, and Data Demodulation - Understanding GPS: Principles and Applications - page 161

change. If the boundary is straddled and there is a data transition, the integration
and dump result for that interval will be degraded. In the worst case, if the data tran-
sition occurs at the halfway point, the signal will be totally canceled for that inter-
val. Usually, during initial C/A code signal search, acquisition, and loop closure, the
receiver does not know where the SV data bit transition boundaries are located
because each C/A code epoch is only 1 ms in duration but the data bit is 20 ms in
duration. Then, the performance degradation has to be accepted until the bit syn-
chronization process locates the data bit transitions. During these times, short
predetection integration times are used in order to ensure that most of the integrate
and dump operations do not contain a data transition boundary. With signals that
have spreading code periods that are as long or longer than the data bit period,
receivers can choose longer predetection time intervals that are aligned with data bit
edges.
As shown in Figure 5.4, the SV data transition boundary usually does not align
with the receiver's 20-ms clock boundary, which will hereafter be called the funda-
mental time frame (FTF). The phase offset is shown as bit sync phase skew . A bit
synchronization process determines this phase offset shortly after the signal has
been acquired when the receiver does not know its position and precise GPS time. In
general, the bit sync phase skew is different for every SV being tracked because even
though the data transitions are well aligned at SV transmit time, the difference in
range to the user causes them to be skewed at receive time. This range difference
amounts to about a 20-ms variation from zenith to horizon. The receiver design
must accommodate these data bit phase skews if an optimum predetection integra-
tion time is used. This optimization is assumed in the generic receiver design, but
some receiver designs do not implement this added complexity. They use short
(suboptimal) predetection integration times.

5.2.3 Digital Frequency Synthesis
In this generic design example, both the carrier and code tracking loops use an NCO
for precision replica carrier and code generation. The NCO provides measurements
that contain negligible quantization noise [1].
One replica carrier cycle and one replica code cycle are completed each time the
NCO overflows. A block diagram of the carrier loop NCO and its sine and cosine
mapping functions are shown in Figure 5.5 [1]. In Figure 5.3, note that there is a
code NCO bias and a carrier NCO bias applied to their respective NCOs. These
biases set the NCO frequency to the nominal code spreading code chip rate and IF
carrier frequency, respectively, because they are constants. As an NCO bias compu-
tational example using the equation for output frequency in Figure 5.5, assume that
the bias is set for the P(Y) code nominal spreading code chip rate of 10.23 MHz.
Assume a 32-bit NCO with a clock f s = 200 MHz, then the code NCO bias is M =

10 8 . This value of M sets the NCO output frequency to
10.23 MHz with a resolution of 200

2 32 /200

10.23 × = 2.1969 ×

10 6 /2 32 0.046566 Hz.

For the carrier NCO, the map functions convert the amplitude of the NCO
staircase output [Figure 5.6(a)] into the appropriate trigonometric functions as
shown in Figure 5.6(b, c). Figure 5.7 illustrates the basic idea of digital frequency
synthesizer design.

× =