Introduction to Multiprocessors - Fundamentals of Computer Organization and Architecture - page 242

Figure 11.4 The Erlangen classification scheme

, k 0 k 0 0 , d 0 d 0 0 , w 0 -

expressed using either of the two subunits is characterized as

w 0 0 . _ , k 1 k 0 1 , d 1 d 0 1 , w 1 w 0 1 . .

For example, a later design of the ILLAC-IV consisted of two DEC PDP-10 as the
front-end controller where data can only be accepted from one PDP-10 at a time.
This version of the ILLAC-IV can be characterized as (2, 1, 36)

0

(1, 64, 64).
Now, since the ILLAC-IV can also work in a half-word mode whereby there are
128 32-bit processors rather than the 64 64-bit processors, then an overall character-
ization of the ILLAC-IV is given by (2, 1, 36)

(1, 128, 32)].
As can be seen, this classification scheme can be regarded as a hierarchical classi-
fication that puts more emphasis on the internal structure of the processing hardware.
It does not provide any basis for the classification and

[(1, 64, 64)

_

or grouping of computer
architectures. In particular, the classification overlooks the interconnection among
different units.

/

11.2.5. Skillicorn Classification Scheme

Owing to its inherent nature, Flynn's classification may end up grouping computer
systems with similar architectural characteristics but with diverse functionality into
one class. This same observation has been the main motive behind the Skillicorn
classification introduced in 1988. According to this classification, an abstract von
Neumann machine is modeled as shown in Figure 11.5. As can be seen, the abstract
model includes two memory subdivisions, instruction memory (IM) and data
memory (DM), in addition to the instruction processor (IP) and the data processor
(DP). In developing the classification scheme, the following possible interconnec-
tion relationships were considered: (IP-DP), (IP-IM), (DP-DM), and (DP-IP).
The interconnection scheme takes into consideration the type and number of con-
nections among the data processors, data memories, instruction processors, and
instruction memories. There may exist no, one-to-many, and many-to-many such