Introduction to Multiprocessors - Fundamentals of Computer Organization and Architecture - page 241

functional units SISD (SISD-M). The MIMD category is further refined into loosely
coupled MIMD (MIMD-L) and tightly coupled MIMD (MIMD-T). The SIMD
category is further refined into word-sliced processing (SIMD-W) and bit-sliced
processing (SIMD-B). Therefore, Hwang and Briggs classification added a level
to the hierarchy of machine classification such that a given machine should be
first classified as SISD, SIMD, MIMD, and then further classified according to its
constituent descendant.
According to the Hwang and Briggs's taxonomy, it is always true to predict that an
SISD-M will perform better than an SISD-S. It is, however, doubtful that such predic-
tion can be made with respect to SIMD-W and SIMD-B. For example, it has been indi-
cated that using the maximum degree of potential parallelism as a performance
measure, then the ILLAC-IV machine (SIMD-W) is inferior to the MPP machine
(SIMD-B). A final observation on the Hwang and Briggs's taxonomy is that shared
memory systems (see Chapter 4 of our topic on Advanced Computer Architecture
and Parallel Processing, see reference list) map naturally into the MIMD-T
category, while nonshared memory systems map into the MIMD-L category.

11.2.4. Erlangen Classification Scheme

In its simplest form, this classification scheme adds one more level of details to the
internal structure of a computer, compared to Flynn's scheme. In particular, this
scheme considers that in addition to the control (CNTL) and processing (ALU)
units, a third subunit, called the elementary logic unit (ELU), can be used to charac-
terize a given computer architecture. The ELU represents the circuitry required to
perform the bit-level processing within the ALU. An architecture is characterized
using a three-tuple system (k, d, w) such that k ¼

number of CNTLs, d ¼ number

of ALU units associated with one control unit, and w ¼ number of ELUs per

ALU (the width of a single data word). For example, in one of its models, the
ILLAC-IV was made up of a mesh connected array of 64 64-bit ALUs controlled
by a Burroughs B6700 computer. According to Erlangen,

this model of the

ILLAC-IV is characterized as (1, 64, 64).
Postulating that pipelining can exist at all three levels of hardware processing, the
classification includes three additional parameters. These are w 0 ¼ the number of

pipeline stages per ALU, d 0 ¼ the number of functional units per ALU, and

k 0 ¼

the number of ELUs forming the control unit. Given the expected multi-unit
nature of each of the three hardware processing levels, a more general six-tuple
can be used to characterize an architecture as follows: (k k 0 , d d 0 , w w 0 ).
Figure 11.4 illustrates the Erlangen classification system.
More complex systems can still be characterized using the Erlangen system
by using two additional operators, the AND operator, denoted by , and the

ALTERNATIVE operator, denoted as . For example, an architecture consisting

of two computational subunits each having a six-tuple (k 0 k 0 0 , d 0 d 0 0 , w 0 w 0 0 )
and (k 1 k 0 1 , d 1 d 0 1 , w 1 w 0 1 ) is characterized using both subunits as (k 0 k 0 0 ,
d 0 d 0 0 , w 0 w 0 0 )

_

(k 1 k 0 1 , d 1 d 0 1 , w 1 w 0 1 ), while an architecture that can be