Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 227

10.6. EXAMPLE OF ADVANCED RISC MACHINES

In this section, we introduce two representative advanced RISC machines. Our
emphasis in this coverage is on the pipeline features and the branch handling mech-
anisms used.

10.6.1. Compaq (Formerly DEC) Alpha 21264

Alpha 21264 (EV6) is a third generation Compaq (formerly DEC) RISC superscalar
processor. It is a full 64-bit processor. The 21264 has an 80-entry integer register file
and a 72-entry floating-point register file. It employs a two-level cache. The L1 data
and instruction caches are 64 KB each. They are organized in a two-way set-associ-
ative manner. The L2 data cache can be 1 to 16 MB (shared by instructions and data)
organized using direct-mapping. The block size is 64 bytes. The data cache can
receive any combination of two loads or stores from the integer execution pipe
every cycle. This is equivalent to having the 64 KB on-chip data cache delivering
16 bytes every cycle, hence twice the clock speed of the processor. The 21264
memory system can support up to 32 in-flight loads, 32 in-flight stores, and 8
in-flight (64 byte) cache block fills and 8 cache misses. It has a 64 KB, two-way
set-associative cache (both instruction and data). It can also support up to two
out-of-order operations (Fig. 10.8).

10.6.2. The Alpha 21264 Pipeline

The Alpha 21264 instruction pipeline is shown in Figure 10.9. It consists of SEVEN
stages. These are the Fetch, Slot Assignment, Rename, Issue, Register Read,
Execute, and Memory stages.
The fetch stage can fetch and execute up to four instructions per cycle. A block
diagram of the fetch stage is shown in Figure 10.10. This stage uses a unique “block
and set” prediction technique. According to this technique, both the locations of the
next four instructions and the set (there are two sets) in which they are located, are
predicted. The “block and set” prediction technique combines the speed advantages
of a direct-mapped cache with the lower miss ratio of a two-way set-associative

Cache L1
(Data 64 KB, 2-way) +

(Instruction 64 KB, 2-way)
(Block size is 64 Byte)
Cache L2 (off-chip)
(Data 1-16 MB, direct)
Main Memory (up to 16 GB)

Hard Disk (100s of Terabytes)

Figure 10.8 The 21264 memory hierarchy