Reduced Instruction Set Computers (RISCs) - Fundamentals of Computer Organization and Architecture - page 226

6 26

Op-Code Jump Target

Figure 10.6 Jump instruction format used in MIPS

jumps, relative jumps, and compare instructions. Only two special flow instructions
were provided. They support procedure and interrupt linkage. Some examples of
MIPS instructions are:

1. ALU: Add src 1 , src 2 , dst; dst src 1 þ src 2
2. Load Store: Ld [src 1 þ src 2 ], dst; dst M[src 1 þ src 2 ]

3. Control: Jmp dst; PC dst
4. Special Function: SavePC A; M[A]

/

PC

MIPS does not provide direct support for floating-point operations. Floating-
point operations are to be done by a specialized coprocessor. Surprisingly,
non-RISC instructions such as MULT and DIV were included and they use special
functional units. The contents of two registers can be multiplied or divided and the
64-bit product is kept in two special registers LO and HI.
Procedure call can be made through the JUMP instruction shown in Figure 10.6.
The instruction uses a 26-bit jump target address.
The MIPS virtual address is 32 bits long, thus allowing for up to four Gwords
virtual address space. A virtual address is divided into a 20-bit virtual page
number and a 12-bit offset within the page. The actual implementation of MIPS
was restricted by packaging constraints allowing only 24 address pins; that is, the
actual physical address space is 2 24 16 Mwords (32 bits each). A support for

off-chip TLB for address translation is provided. The MIPS organization is shown
in Figure 10.7.

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Figure 10.7 MIPS organization