Input–Output Design and Organization - Fundamentals of Computer Organization and Architecture - page 170

User Processes

I/O Reply

I/O Request

Device Independent Software

Device Drivers

Interrupt Handlers Wakeup driver when I/O is done

Hardware Perform I/O

Figure 8.7 Layered I / O software

Figure 8.7 shows the layers of software involved in I O operations. First, the pro-

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gram issues an I O request via an I O call. The request is passed through to the I O

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device. When the device completes the I O, an interrupt is sent and the interrupt handler

is invoked. Eventually, control is relinquished back to the process that initiated the I

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O.

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Example 1: 80 3 86 Interrupt Architecture

86 processors have just
two hardware interrupt pins. These are labeled INTR and NMI. NMI is a nonmaskable
interrupt, which means it cannot be blocked and the processor must respond to it. The
NMI input is usually reserved for critical system functions. The INTR input is a mask-
able interrupt request line between the CPU and the programmable interrupt controller
(8259A PIC). Interrupts on INTR can be enabled and disabled using the instructions
STI (set interrupt flag) and CLI (clear interrupt flag), respectively.
Interrupt handlers are called interrupt service routines (ISR). The address of each
interrupt service routine is stored in four consecutive memory locations in the inter-
rupt vector table (IVT). The IVT stores pointers to ISR for each type of interrupt.
When an interrupt occurs, an 8-bit type number is supplied to the processor,
which identifies the appropriate entry in this table.
When an interrupt is generated by a device, it goes to the PIC. Multiple interrupts
may be generated simultaneously. However, they are all buffered by the PIC. The
PIC decides which one of these interrupts should be forwarded to the CPU. To
inform the CPU that an outstanding interrupt is waiting to be processed, the PIC
sends an interrupt request (INTR) to the CPU, which then, at the appropriate
time, responds with an interrupt acknowledgment (INTA). At this time, PIC will
put an 8-bit interrupt type number associated with the device on the bus so that
the CPU can identify which interrupt handler to invoke. In the case when several
interrupts are pending, PIC will send next interrupt request to the CPU only after
it receives an end of interrupt command from the current ISR. Figure 8.8 shows
the simple protocol that is used to determine which ISR is to be invoked.
In the computer designs that used a single PIC (PC and XT), eight different inter-
rupt requests are allowed (IRQ0-IRQ7). Table 8.1 shows a list of standard interrupt
type numbers for typical devices. When AT was designed, a second PIC was added,

The 80