Input–Output Design and Organization - Fundamentals of Computer Organization and Architecture - page 167

O devices has access to the interr upt l ine INR.
Upon recognizing the arrival of a request (called Interrupt Request) on INR, the pro-
cessor polls the devices to determine the requesting device. This is done through
the

In the figure, each of the N I

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polling lines. The priority of the requesting device will determine the
order in which addresses are put on the polling lines. The address of the highest priority
device is put first, followed by the next priority, and so on until the least priority device.
In addition to the I

d Log 2 N e

O
operations. These are interrupt-driven I / O and direct memory access (DMA). These
are discussed in the next two sections.

O polling, two other mechanisms can be used to carry out I

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8.3. INTERRUPT-DRIVEN I / O

It is often necessary to have the normal flow of a program interrupted, for example, to
react to abnormal events, such as power failure. An interrupt can also be used to
acknowledge the completion of a particular course of action, such as a printer indicating
to the computer that it has completed printing the character(s) in its input register and
that it is ready to receive other character(s). An interrupt can also be used in time-sharing
systems to allocate CPU time among different programs. The instruction sets of modern
CPUs often include instruction(s) that mimic the actions of the hardware interrupts.
When the CPU is interrupted, it is required to discontinue its current activity,
attend to the interrupting condition (serve the interrupt), and then resume its activity
from wherever it stopped. Discontinuity of the processor's current activity requires
finishing executing the current instruction, saving the processor status (mostly in the
form of pushing register values onto a stack), and transferring control (jump) to what
is called the interrupt service routine (ISR). The service offered to an interrupt will
depend on the source of the interrupt. For example, if the interrupt is due to power
failure, then the action taken will be to save the values of all processor registers and
pointers such that resumption of correct operation can be guaranteed upon power
return. In the case of an I O interrupt, serving an interrupt means to perform the

required data transfer. Upon finishing serving an interrupt, the processor should
restore the original status by popping the relevant values from the stack. Once the
processor returns to the normal state, it can enable sources of interrupt again.
One important point that was overlooked in the above scenario is the issue of ser-
ving multiple interrupts, for example, the occurrence of yet another interrupt while
the processor is currently serving an interrupt. Response to the new interrupt will
depend upon the priority of the newly arrived interrupt with respect to that of the
interrupt being currently served. If the newly arrived interrupt has priority less
than or equal to that of the currently served one, then it can wait until the processor
finishes serving the current interrupt. If, on the other hand, the newly arrived inter-
rupt has priority higher than that of the currently served interrupt, for example,
power failure interrupt occurring while serving an I

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O interrupt, then the processor
will have to push its status onto the stack and serve the higher priority interrupt.
Correct handling of multiple interrupts in terms of storing and restoring the correct
processor status is guaranteed due to the way the push and pop operations are

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