Memory System Design I - Fundamentals of Computer Organization and Architecture - page 129

Figure 6.13 Division of main memory address

2 18 2 7 2 11 blocks

Number of cache blocks N ¼ = ¼

2 11 2 3 2 8 S ¼ = ¼ sets

log 2 2 8

Set field ¼ ¼ 8 bits

log 2 2 7 Word field ¼ log 2 B ¼ log 2 128 ¼ ¼ 7 bits

log 2 (2 17 2 8 ) Tag field ¼ / ¼ 9 bits

The following tables summarize the L1 and L2 Pentium 4 cache performance in
terms of the cache hit ratio and cache latency.

L1 Hit
ratio

L2 Hit
ratio

L1
Latency

L2
Latency

Average
latency CPU

Pentium 4 at 1.5 GHz 90% 99% 1.33 ns 6.0 ns 1.8 ns

PowerPC 604 Processor Cache The PowerPC cache is divided into data and
instruction caches, called Harvard Organization. Both the instruction and the data
caches are organized as 16 KB four-way set-associative. The following table sum-
marizes the PowerPC 604 cache basic characteristics.

Cache organization Set-associative

Block size 32 bytes

Main memory size 4 GB (M ¼ 128 Mega blocks)

Cache size 16 KB (N ¼ 512 blocks)

Number of blocks per set Four

Number of cache sets (S) 128 sets

The main memory address should be divided into three fields: Word, Set, and Tag
(Fig. 6.13). The length of each field is computed as follows:

2 32 2 5 2 27 blocks

Number of main memory blocks M ¼ = ¼

2 14 2 5 Number of cache blocks N ¼ = ¼ 512 blocks

S ¼ 512 = 4 ¼ 128 sets

Set field ¼ log 2 128 ¼ 7 bits

log 2 2 5

Word field ¼ log 2 B ¼ log 2 32 ¼ ¼ 5 bits

log 2 (2 27 2 7 ) Tag field 20 bits

¼ / ¼

log 2 (2 5 2 27 )

Main memory address log 2 (B M) 32 bits

¼ ¼ ¼