Memory System Design I - Fundamentals of Computer Organization and Architecture - page 130

PMC-Sierra RM7000A 64-bit MIPS RISC Processor The RM7000 uses a

different cache organization compared to that of the Intel and the PowerPC. In
this case, three separate caches are included. These are:

1. Primary instruction cache: A 16 KB, four-way set-associative cache with
32-byte block size (eight instructions)
2. Primary data cache: A 16 KB, four-way set-associative cache with 32 bytes
block size (eight words)
3. Secondary cache: A 256 KB, four-way set-associative cache for both instruc-
tions and data

In addition to the three on-chip caches, the RM7000 provides a dedicated tertiary
cache interface, which supports tertiary cache sizes of 512 KB, 2 MB, and 8 MB.
This tertiary cache is only accessed after a secondary cache miss.
The primary caches require one cycle each to access. Each of these caches has
64-bit read data path and 128-bit write data path. Both caches can be accessed sim-
ultaneously, giving an aggregate bandwidth of over 4 GB per second. The secondary
cache has a 64-bit data path and is accessed only on a primary cache miss. It has a
three-cycle miss penalty. Owing to the unusual cache organization of the RM7000, it
uses the two cache access schemes described below.

Non-Blocking Caches In this scheme, the caches do not stall on a miss, rather the

processor continues to operate out of the primary caches until one of the following
events takes place:

1. Two cache misses are outstanding and a third load store instruction appears

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on the instruction bus.
2. A subsequent instruction requires data from either of the instructions that
caused a cache miss.

The use of nonblocking caches improves the overall performance by allowing the
cache to continue operating even though a cache miss has occurred.

Cache Locking In this scheme, critical code or data segments are locked into the pri-

mary and secondary caches. The locked contents can be updated on a write hit, but
cannot be selected for replacement on a miss. RM7000 allows each of the three
caches to be locked separately. However, only two of the available four sets of each
cache can be locked. In particular, RM7000 allows a maximum of 128 KB of data or
code to be locked in the secondary cache, a maximum of 8 KB of code to be locked
in the instruction cache, and a maximum of 8 KB of data to be locked in the data cache.

6.3. SUMMARY

In this chapter, we consider the design and analysis of the first level of a memory
hierarchy, that is, the cache memory. In this context, the locality issues were