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Fig. 6.
3
Conclusions
This paper discusses a method to model the gate input capacitance for accurate STA.
For static timing analysis, we have to model the gate input capacitance, which gives
the best characteristic of a given gate. Siliconsmart derives the equivalent capacitance
by integrating over the full transition range or 20-80 transition range of the applied
input signal. Conventionally, average of all input pin capacitance considered for all
input slew and output load condition. However, this capacitance is less than the actual
capacitance. Also, in some cases of traditional method, the capacitance is the
maximum capacitance across all input slew/load; and it results pessimistic delay. The
pessimistic delay estimation is reasonable for checking setup time constrains, but it
can cause hold violation.
The proposed method derives the characteristic capacitance of logic gate and gives
the most optimum input cap of the given gate. The result shows good correlation
using LC Liberty Vs Traditional Liberty.
References
1.
Kouno, T., Hashimoto, M., Onodera, H.: Dept. Communications and Computer Engineering.
Kyoto University, Dept. Information Systems Engineering, Osaka University Input
Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis
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microprocessor. Journal of Solid-State Circuits 33, 1627-1633 (1998)
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Singhal, V., Bittlestone, C., Hill, A., Arvind, N.V.: Architecting asic libraries and flows in
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4.
Subramaniam, P.: Modeling MOS VLSI circuits for transient analysis. Journal of Solid-State
Circuits 21, 276-285 (1986)
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Synopsys. SiliconSmart
TM
ACE Version (June 2012)
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Synopsys. PT Static Time Analysis
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Synopsys “CCS Timing White paper” (1996)
