An Area Efficient Wide Range On-Chip Delay Measurement Architecture - VLSI Design and Test - page 49

An Area Ecient Wide Range On-Chip Delay
Measurement Architecture
Rahul Krishnamurthy and G.K. Sharma
ABV-Indian Institute of Information Technology and Management
National Highway #92, Gwalior - 474 015(M.P.), India
[e-mail], [e-mail]
Abstract. Aggressive design practices in nanoscale era has led to an
increase in the performance of circuit at the cost of reduced slack margins.
Reduced margin increases the risk of path failures due to small additional
delays. In this paper, an on-chip path delay measurement architecture
is designed to identify paths which violates timing constraints. A new
method of measuring delay based on crossovers is proposed. Simulation
results show precise measurement of path delays. Maximum path delay
measured by the proposed architecture is 4.3 times the maximum delay
measured by Modified Vernier Delay Line (MVDL) architecture and the
area is 74% less than the area of MVDL.
Keywords: Time to Digital converter, Vernier Delay Line, Path Delay
Characterization.
1 Introduction
In advanced CMOS technology, detection of timing related failures has become
primary testing challenge. Increasing gap between the operating frequency of cir-
cuits and external Automatic Test Equipments(ATEs) has compelled researchers
to design on-chip circuits which will assist detection of delay defects. An on-chip
delay sensor proposed in [7], converts time-to-voltage to measure path delays.
Drawback of this technique is its dependence on the voltage across a capacitor
which may vary due to leakage.
Another on-chip technique to detect delay defects is to use a Time to Digi-
tal converter(TDC). In [3], a single delay line TDC is embedded in one core of
System-on-Chip(SOC). That core is dedicated for the purpose of detecting de-
lay defects in neighbouring cores and interconnects. However, precision of delay
measurement in a single delay line TDC is limited by the minimum gate delay.
In [4], a Modified Vernier Delay Line (MVDL) architecture using scan flip-
flops is designed to facilitate detection of small delay and gross delay faults. The
major drawback of MVDL is the trade-off that exist between the number of
stages and the minimum delay that can be measured. Smaller delay range of a
stage gives a high precision measurement. However, to detect delays over a wide
range, a large number of stages will be required. This increases the area overhead
and reduces the accuracy of measurement, as the long delay lines are susceptible