Information Technology Reference
In-Depth Information
Parameters
L
1
norm
L
2
norm
Bi-diag
Number of Slice Registers*
32
97
137
Number of Slice LUTs ** 32
66
76
Number used as Logic ** NA
2
12
Number of LUT FF pairs used
64
98
213
Number of bonded IOBs ***
97
97
65
(* out of 1268000, ** out of 63400, *** out of 210)
Note
1
Design Summary of Sum1, Sum2, Squareroot:
Selected Device: xa7a100tcsg324-2i.
Parameters
Sum1
Sum2
Squareroot
Number
of
Slice
65
240
282
Registers*
Number of Slice LUTs ** 1
117
67
Number used as Logic ** 1
53
67
Number of LUT FF pairs
used
66
253
304
Number of bonded IOBs
***
64
161
97
(* out of 1268000, ** out of 63400, *** out of 210)
SVD:
The SVD implementation is done using various synthesized Architectural entities
given above. The
Table 1
gives comparison of first diagonal element of 'S' Matrix
(equation (2)) of VHDL implementation and Matlab implementation, though we have
the complete Matrix (U, S, V) available, the first diagonal element being the dominant
value of SVD is used for comparison in the table. We compared the timing for our
SVD calculation to the implementation in [15] for size 16 X 32 and have found to be
faster by a factor of 2.7. Our implementation for 32X16 takes 1.969 ms while
implementation given in [15] takes 5.344 ms. The clock period used is 10 ns for
getting the results but it can be reduced to 3 ns as lower limit, so the above values in
the table can reduce to 1/3
rd
.
The Xilinx ISE value and the Matlab value indicated in the table are output of SVD
for various sample input vectors. The ISE values and Matlab values are observed to
be almost same and the error is negligible compared to implementation done by [15]
which has error of around 1.4% for first diagonal element for 16X32 size.
1
The device summary does not add the hardware resources used by FP core. The resource
utilization for Artix7 is available in the document, LogiCORE IP Floating-Point Operator
v6.2 Product Guide PG060 December 18, 2012.
