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In-Depth Information
In Fig. 3, as noted above,
the amplifier gain is varied by controlling the currents
through
M
13
and M
14
. Hence the currents through
M
7
and M
8
must also vary as a
function of the control voltage. A common-mode feedback (CMFB) circuit [2] is used
to prevent any transistor from entering the triode region and to maintain a constant
common-mode output voltage, as the control voltage varies.
4
Simulation Results
The proposed VGA circuit was designed in a standard 0.18
ΚΌ
m CMOS technology.
Simulations were carried out in LT-Spice. V
DD
was 1.2 V, and V
SS
was 0 V.
The frequency response of the VGA for different gains is shown in Fig. 4. For a
maximum gain of 25 dB, the bandwidth is 110 MHz. The bandwidth increases with
reduction in gain. At the minimum gain of -32 dB, the bandwidth is 3828 MHz.
Fig. 4.
Frequency Response of the Proposed VGA at different Gain Settings
The simulated performance of the VGA is shown in Table I. The Table also compares
the proposed VGA with similar VGA's reported in the literature. The Table shows that
the proposed VGA achieves the best performance in terms of the dynamic range of the
gain variation, power consumption, and bandwidth, for a single-stage circuit.
5
Conclusion
A CMOS VGA with a high bandwidth and low-power consumption is proposed. The
proposed circuit uses a capacitive neutralization technique to achieve wideband
operation, and parallel driver and load paths for the dc currents of the differential
amplifier. With an exponential approximation function a wide decibel linear range is
achieved, so that only a single VGA stage is needed.
