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On Designing Testable Reversible Circuits
Using Gate Duplication
Joyati Mondal
1
, Debesh Kumar Das
1
,DipakKumarKole
2
,
Hafizur Rahaman
3
, and Bhargab B. Bhattacharya
4
1
Jadavpur University
{
joyatimondal14,debeshkdas
}
@gmail.com
2
St. Thomas' College of Engg. & Tech.
dipak.kole@gmail.com
3
Bengal Engineering and Science University
rahaman h@yahoo.co.in
4
Indian Statistical Institute
bhargab.bhatta@gmail.com
Abstract.
Design of reversible logic circuits has received considerable attention
in recent times for their potential use in implementing quantum computers. In this
paper, it is shown that in an (
n×n
) reversible circuit implemented with
k
-CNOT
gates, addition of only two extra inputs along with at most 5
k
-CNOT gates per
gate can yield an easily testable design. The modified design admits a universal
test set of size (
n
+2)that detects all SMGFs, PMGFs, and detectable RGFs in
the circuit.
Keywords:
Quantum computing, reversible logic, testable design.
1
Introduction
Management of energy loss has been an inherent problem in digital logic circuits, espe-
cially because of exponential growth in the number of transistors in integrated circuits
[5]. According to Landauer's principle, irreversibility of information processing causes
energy loss [1]. Reversible circuits, being information lossless, are likely to consume
less energy. Also, with the advent quantum computing, synthesis of reversible circuits
has drawn considerable attention in recent times [7-9].
Understanding of fault model and errors in a reversible circuit is an important con-
cern from the viewpoint of dependability. Several fault models for these circuits were
introduced in [2,6], namely Single Missing Gate Faults (SMGF), Partial Missing Gate
Faults (PMGF), and Repeated Gate faults (RGF). In this paper, we propose a design-
for-testability (DFT) technique to detect these faults. We make an (
n
n
) reversible
circuit implemented with
k
-CNOT gates easily testable by adding only two extra input
lines and some extra gates so that so that all such faults are detected by a universal test
set of size (
n
+2). Our DFT scheme offers a significant reduction in quantum cost
compared to an earlier work [4].
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