Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals - VLSI Design and Test - page 321

Table 2. Comparison of estimated time for evaluating leakage current

Mode of
Operation

Time taken by
Hspice Simulator

Time taken by the
proposed model

Improvement in speed by our
model over HSPICE result

Idle Phase 1.062057 Sec 7.387 msec 143 times

Read Phase 0.706034 Sec 5.537 msec 127 times

Write Phase 1.455412 Sec 4.412 msec 330 times

6 Conclusion

In our work, we have estimated the width dependent leakage current of SRAM core at
an early stage. We have proposed an analytical model of SRAM based on its mode of
operation and structure .The proposed model have been compared with the design
mentioned in [1] and the actual results (HSPICE simulation) .Our work shows higher
accuracy than previous work with an error margin less than 5%.The timing analysis
shows that our results obtained are many folds faster than the golden results.

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