Information Technology Reference
In-Depth Information
Fig. 1.
Flow at IP level
4
ip_tb_gen Tool
Ip_tb_gen is a tool for automatic testbench generation. The verification methodology
followed is UVM while currently it supports System Verilog as HVL. This language
and methodology is chosen because this is the most adopted combination in the
industry and all the major EDA vendors are supporting this. The configuration and
connection is also quite easy without touching the underlying components.
The tool takes following as input:
•
Name of the top level design block.
•
VIP definition of a particular protocol which includes the name of VIP and
following tabular definition files :
•
Interface connectivity CSV: This will include interface connectivity information
to DUT such as name of instance, name of testbench, input/output directions etc.
•
Configuration settings CSV
:
This will include configuration settings related
to VIP
•
Mode of using VIP: either as master or slave.
•
Type of VIP
:
Existing/Non-existing
•
Name of top clock and reset signal.
•
Name of simulator to be used.
