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C
5
2
C
W
L
W
L
cedure, we obtain the sizes for the current source/s
rs in the ring oscillator.
From the above proc
transistors and inverter
sink
4
Simulation Resu
ults
The design method given in
transistors for three stage c
frequency of 404.5 MHz.
UMC 0.18 µm process par
Fig. 5. It is observed from F
V characteristic as compa
percentage non-linearity o
design method. The linear f
indicates that the method is
n section 3 is implemented to calculate the aspect ratios
current starved ring VCO (shown in Fig. 1) with a cen
Spectre simulation results for the design implemented
rameters at 1.8 V supply voltage are shown in Fig. 4.
Fig. 4. that the proposed design method shows a linear
ared to conventional design method. Fig. 5. shows
of f
osc
-V
control
characteristic obtained from the propo
f-V characteristic for N=5 and N=7 stages shown in Fig
independent of number of stages.
s of
nter
d in
and
f-
the
osed
g. 6.
1.0G
800.0M
600.0M
400.0M
200.0M
Proposed
Conventio
Calculate
d Method
onal Method
ed
0.0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Vcontrol (V)
Fig. 4.
Linearity compar
conventional vs. proposed de
rison of
esign method
Fig. 5.
% non-linearity of f
osc
-V
control
for th
proposed design method
he
450.0
0M
400.0
0M
N=5
350.0
0M
300.0
0M
N=7
250.0
0M
200.0
0M
150.0
0M
100.0
0M
50.0
0M
0
0.0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Vcontrol (V)
Fig. 6.
.
Linearity of f
osc
-V
control
for N=5 and N=7
