Information Technology Reference
In-Depth Information
The summary of the tra
shown in Table 1 and Tabl
layout and schematic sim
corresponding layout of the
ansistor sizes and simulation performance parameters
le 2 respectively. Fig. 7(a). shows the comparison of po
mulation of three stage CSVCO. Fig. 7(b). shows
e three stage CSVCO.
are
ost-
the
1.0G
800.0M
600.0M
400.0M
Extracted
Schematic
200.0M
0.0
0.6
0.8
1.0
1
.2
1.4
1.6
1.8
Vcont
trol (V)
(a
Fig. 7.
(a) Comparison of po
stage current starved ring VCO
a)
(b)
ost-Layout simulation and schematic simulation (b) Layout o
O
of 3
Table 1.
Summary of desig
gn parameters
Table 2.
Simulated performance of CSV
VCO
Parameters
Value
Parameters
Value
W
pb
2.40 µm
Technology
0.18 µm
Bias stage transistors
W
nb
0.24 µm
Supply Voltage
1.8 V
W
ps
2.40 µm
Current (I
bias
) @ (f
0
)
88 µA
Current Source /
Sink Transistors (CSTs)
W
ns
0.24 µm
Oscillation
centre
404.5 MHz
frequency (f
0
)
W
p
5.87 µm
Tuning Range
66 - 875 MH
z
Current starved inverters
W
n
2.94 µm
% Full Scale Non-
Linearity
5.567%
Channel length
L
0.18 µm
Power dissipation
@ (f
0
)
260 µW
Table 3.
Comparison
of the simulation results with work reported in literature
Parameters
Technology (µm)
Supply Voltage (V)
Power (mW)
Center frequency
(MHz
)
Tuning range (
MHz
)
Linearity
Phase Noise (@1 MHz o
Figure of Merit (FOM)
[11]
[1]
This Work
3
0.18
0.18
5.0
2.0
1.8
150
22
0.26
10
390
404.5
1 - 15
20 - 807
66 - 875
99.8%
-
94.5%
offset)
-
-108 dBc/Hz
-82.28 dBc/Hz
-
-
-140.27 dBc/Hz
