CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions - VLSI Design and Test - page 239

ʱ-max calculation state, where the intersection point of the segments is calculated.
The intersection points are stored in the ʱ -memory. Rule activation is performed in
the rule strength calculation state. The rule strength is stored in the φ register, which
is then used in the X calculation state to obtain the consequence X . In the next state, φ
and X , for each rule are multiplied and accumulated to get ∑ and ∑ . The

controller then passes onto the defuzzification state, which performs Yager's defuzzi-
fication to get the crisp output Z o .

3 Simulation and Results

The circuit has been designed in 45 nm using NCSU PDK and OSU standard cell
library. RTL synthesis has been done using the Cadence Encounter RTL Compiler.
The simulations have been performed in Cadence Virtuoso Spectre Circuit Simulator.
The circuit for the processor is shown in Fig. 8.
The circuit is designed to operate at a frequency of 2 GHz using a power supply of
1 V. Kogge-Stone adders have been used in the design. The power and delay of the
circuit with respect to the number of active rules are presented in Table 1. As the
number of active rules increases, the computation time and the energy dissipation of
the rule unit increase. Thus there is an increase in delay with the increase in number
of active rules. The computation time and the energy dissipation of detection unit,
antecedent unit and defuzzifier are independent of the number of active rules. The
contribution of these three units to average power dissipation decreases with the in-
crease in delay, since the average is calculated over delay. Thus lesser delay results in
higher average power dissipation. Thus the power dissipation increases with the de-
crease in number of active rules.

Table 1. Power and delay of circuit Table 2. Comparison of the processors

No. of
active rules

Power (mW) Delay (ns)

Fuzzy processor Power (W) Delay (ns)

8 123.9 260

Proposed ASIC 0.124 260

16 104.7 355

32 86.5 545

ARM 922T 0.5 2500

64 84.4 605

Pentium IV 71.8 60000

128 71.7 1045

256 70.5 1285

The performance of the proposed ASIC has been compared with the performances
of fuzzy processors based on RISC (200 MHz ARM 922T) and CISC (2 GHz Pen-
tium IV) architectures [15] for 8 active rules in Table 2. The proposed circuit has
much less power dissipation and delay compared to the general purpose processors.