CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions - VLSI Design and Test - page 240

Conclusion

4

The current work describes the ASIC design of a high speed fuzzy processor. The
processor can work on different membership functions. The architecture exploits pi-
pelining and parallelism to reduce the inferencing delay. The processor has been de-
signed to operate at a frequency of 2 GHz using a power supply of 1 V . For a system
with 256 active rules, the circuit has delay of 1285 ns and power dissipation of 70.5
mW. Storing the set of common antecedents for a group of rules separately leads to
reduction in delay and power dissipation. The circuit has lesser power dissipation and
delay compared to state of the art RISC and CISC architecture processors.

Acknowledgments. The authors would like to acknowledge the support lent by the
Department of Science and Technology, Govt. of India and the Ministry of Human
Resource Development, Govt. of India for providing the necessary fund and resources
needed to carry out the research work.

References

1. Togai, M., Watanabe, H.: Expert System on a Chip: An Engine for Real-Time Approx-
imate Reasoning. IEEE Expert Systems Magazine 1(3), 55-62 (1986)
2. Lim, M.H., Takefuji, Y.: Implementing fuzzy rule-based systems on silicon chips. IEEE
Expert Systems Magazine 5(1), 31-45 (1990)
3. Zadeh, L.A.: Outline of a New Approach to the Analysis of Complex Systems and Deci-
sion Processes. IEEE Transactions on Systems, Man and Cybernetics 3(1), 28-44 (1973)
4. Zadeh, L.A.: Fuzzy logic, neural networks and soft computing. ACM Transactions on
Computing 37(3), 77-84 (1994)
5. Surmann, H., Ungering, A.P.: Fuzzy rule-based systems on general purpose processors.
IEEE Micro 15(4), 40-48 (1995)
6. Watanabe, H., Detloff, W.D., Symon, J.R., Yount, K.E.: VLSI fuzzy chip and inference
accelerator board systems. In: Fuzzy Logic for Management of Uncertainty, pp. 211-243.
Wiley, New York (1992)
7. Nakamura, K., Sakashita, N., Nitta, Y., Shimomura, K., Tokuda, T.: Fuzzy inference and
fuzzy inference processor. IEEE Micro 13(5), 37-48 (1993)
8. Manzoul, M.A., Tayal, S.: Systolic VLSI array for multi-variable fuzzy control systems.
International Journal of Systems and Cybernetics 21(1), 27-42 (1990)
9. Jaramillo-Botero, A., Miyake, Y.: A high speed parallel architecture for fuzzy infer-ence
and fuzzy control of multiple processes. In: Proceedings of IEEE 1994 World Congress on
Computational Intelligence, vol. 3, pp. 1765-1770 (1994)
10. Orsila, H., Kangas, T., Salminen, E., Hamalainen, T.D., Hannikainen, M.: Automated
memory-aware application distribution for Multi-processor System-on-Chips. Journal of
Systems Architecture 53(11), 795-815 (2007)
11. Samoladas, V., Petrou, L.: Special-purpose architectures for fuzzy logic controllers. Mi-
croprocessing and Microprogramming 40(4), 275-289 (1994)
12. de Salvador, L., Gutierrez, J.: A multilevel systolic approach for fuzzy inference hardware.
IEEE Micro 15(5), 61-71 (1995)