An Improved gm/ID Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design - VLSI Design and Test - page 137

3. Cortes, F., Fabris, E., Bampi, S.: Analysis and design of comparators in CMOS 0.35
μ m technology. Microelectronics Reliability 44, 657-664 (2004)
4. Ferreira, L., Pimenta, T., Moreno, R.: An ultra-low voltage ultra-low power CMOS
Miller OTA with rail-to-rail input/output swing. IEEE Trans. Circuits and Systems-
II 45, 843-847 (2007)
5. Taur, Y., Ning, T.: Fundamentals of Modern VLSI Devices. Cambridge Univ. Press
(1998)
6. Tsividis, Y., McAndrew, C.: Operation and Modeling of The MOS Transistor, 2nd
edn. Oxford University Press (2010)
7. Allen, P., Holberg, D.: CMOS Analog Circuit Design. Oxford University Press (2004)
8. Dunga, M., et al.: BSIM 4.6.0 MOSFET Model-User's Manual. Department of Elec-
trical Engineering and Computer Sciences, University of California, Berkeley (2006)
9. Zhao, W., Cao, Y.: New Generation of Predictive Technology Model for Sub-45
nm Early Design Exploration. IEEE Transactions Electron Devices 53, 2816-2823
(2006)