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(a) Gain Plot of the design with our
methodology..
(b) Phase Plot of the design with our
methodology.
Fig. 7.
Gain and Phase Plot
The OTA circuit is designed for the same specification and the channel length
using the present methodology. The specifications are satisfied with two itera-
tions. For these two iterations, the results are summarized in Table. 2. The AC
analysis plots for the design with our methodology are shown in Fig.7(a), 7(b).
The final simulation results are tabulated in Table. 3. It is observed that the
design with our methodology satisfies all the desired specifications even at the
channel length of 100nm.
5Con lu on
The traditional
g
m
/I
D
methodology does not consider the variations of the Early
voltage of the transistor with the operating bias points. The Early voltage is kept
constant for a particular channel length. However, in the nano-scale domain, the
Early voltage significantly depends upon the drain bias due to the combined
effects of channel length modulation and DIBL phenomenon. This has been ex-
tensively studied in the present work in the 45-nm CMOS technology. By taking
this variation of the Early voltage with the operating bias points, into consider-
ations an improved
g
m
/I
D
methodology has been proposed. The methodology
has been demonstrated with a numerical results.
References
1. Magnelli, L., et al.: Design of a 75-nW, 0.5V subthreshold complementary metal-
oxide-semiconductor operational amplifier. Int. Journal Circuit Theory and Appli-
cations (2013)
2. Silveira, F., Flandre, D., Jesper, P.: A
g
m
/I
D
-based Methodology for the Design of
CMOS Analog Circuits and its Application to the Synthesis of a Silicon-on-Insulator.
IEEE Journal Solid State Circuits 31, 1314-1319 (1996)
