Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology - VLSI Design and Test - page 101

subthreshold region is proposed but it is not robust as the process variations greatly
affect the minimum energy point whereas, in [5] a 32-bit bridge style adder in 32nm
technology is proposed which has considerable improvement in power consumption.
Twelve different subthreshold 1-bit full adders are used for designing 4-bit adders
using Carry-Ripple and Carry Look-Ahead adders in 65nm and 90nm CMOS tech-
nology node [6] and the best adder is determined by comparing different performance
metrics.
In subthreshold circuit design the functionality can be compromised without proper
design for PVT variations. Before exploring the performance metrics for an inverter
we first demonstrate the challenges of designing a circuit in subthreshold region.
Then, the Monte-Carlo Simulation for 100 points was done for inverter for different
channel length and frequency in UMC180nm at 350mV supply voltage. Based on
this, we have designed a 32-bit KS adder in subthreshold region using UMC180nm
and UMC90nm technology. The design was simulated for all five corners with tem-
perature ranging from 0 0 C to 100 0 C. The robustness of the adder is shown through
Monte-Carlo analysis done for 100 point in UMC180nm technology. The same adder
circuit was simulated in UMC90nm technology at 200mV power supply, to show a
comparison in terms of average power, worst-case-delay and power-delay-product.

2 Delay Challenges of Subthreshold Design

2.1 Delay

The first and foremost challenge of circuit operation in the subthreshold region is the
relatively weak current flow resulting in longer delays and lower frequencies. Using a
combination of above-threshold and subthreshold circuits for different components of
the same system provides one means of bypassing this limitation. Another possibility
is lowering the supply voltage while a system is in “standby” or low performance
mode.

2.2 Low Voltage Operation

Operation in the subthreshold region for an inverter in UMC 90nm technology is li-
mited by a minimum operating voltage. This voltage has been calculated to be 3 to 4
V TH (V TH , the thermal voltage is equal to kT/q) . This degradation of circuit operation
at lower Vdd values is shown in Fig. 1. The gain of the VTC lowers for lower values
of Vdd, until it approaches loss of functionality at Vdd=70mV.