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Performance Analysis of Subthreshold 32-Bit
Kogge-Stone Adder for Worst-Case-Delay and Power
in Sub-micron Technology
Himadri Singh Raghav
1,*
, Sachin Maheshwari
2
, and Brahmadeo Prasad Singh
1
1
Faculty of Engineering and Technology, MITS Lakshmangarh, India
{himadri.singh.raghav,sachin.mahe}@gmail.com
2
Department of Electrical and Electronics Engineering, BITS, Pilani, India
bpsingh@ieee.org
Abstract.
Subthreshold logic operation can drastically reduce power, if the de-
creased frequency operation is of secondary importance. In this paper, a 32-bit
Kogge-Stone (KS) adder, which is a basic functional unit of most computation-
al platforms, in sub-threshold logic using UMC 180nm and UMC90nm CMOS
technology is presented. The performance parameters of the adder such as aver-
age power, worst-case-delay and power-delay-product at all five corners with
temperature ranging from 0
0
C to 100
0
C are investigated. The 32-bit adder is
simulated using Spectre Simulator in Cadence environment. Finally, Monte-
Carlo Simulation was done to calculate the worst case delay for 180nm CMOS
Technology.
Keywords:
average power, kogge-stone, low power, sub-threshold, worst-case-
delay.
1
Introduction
A large number of sensors and medical applications like hearing-aids, pacemakers,
and other implantable devices demand ultralow power consumption, so that the user
does not have to recharge or replace the batteries often. Therefore, the robustness of
the device is very challenging in this situation. The main factor in subthreshold design
is maintaining a good trade-off between power consumption, performance and
robustness.
A paper by Kwong and Chandrakasan reported that upsizing is necessary to
achieve robustness at reduced voltages and proposed a design methodology to meet
yield constraints but at the expense of increased energy consumption in the sub-
threshold region [1]. EKV models the short channel effects accurately for deep sub-
micron devices even at subthreshold operation (Vgs < Vt).EKV model has been used
to reduce power consumption when compared to BSIM4 model for 8-bit RCA's in
32nm predictive technology [2]. In [3] multi-operand adder architecture and in [4]
low power energy-efficient 32-bit carry skip adder in 45nm predictive technology in
*
Corresponding author.
