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respectively. Where,
i
next
=
i
curr
+
uf
.
S
LU inter
is the total number of
0
−
to
−
1
and
1
0
bit transitions on the address bus of the data memory, which
takes place due to the last memory address reference (of
a
[
i
curr
+
uf
−
to
−
−
1]) in the
(
uf
+1)
th
iteration (current iteration), and the first memory address reference (of
a
[
i
next
]) in the (
uf
+2)
th
iteration (next iteration). Let,
b
a
[
i
curr
+
uf−
1]
,
b
a
[
i
next
]
,
b
a
[
i
curr
+
u
2
]
be the portion (bits) of the address of array elements
a
[
i
curr
+
uf
1],
a
[
i
next
],
a
[
i
curr
+
u
2
], rescpectively, which are involved in inter-iteration switching
activity. Figure 3 shows the inter-iteration switching on the address bus of data
memory for first eight iterations of
LU
and
LUG
in Fig. 2 (b) and (c), respec-
tively, where,
uf
=16 and
base address
(
a
)=0.
S
LU inter
can be obtained from
Fig. 4. Figure 4(a) shows the inter-iteration switchings for each iteration (from
iteration 1 to iteration 2
ʳ
−
1). In Fig. 4(b) the total inter-iteration switching in
mentioned iteration ranges forms a series whose summation forms the
S
LU inter
.
This can be written as,
S
LU inter
=
ʲ
−
(2
0
+2
1
+2
2
+
+2
ʳ−
2
+2
ʳ−
1
)+
×
···
(2
1
+2
2
+2
3
+
+2
ʳ−
1
+2
ʳ
)
(2
ʳ
1) + (2
ʳ
+1
···
−
ʳ
=
ʲ
×
−
−
2)
−
ʳ
. The final
expression for
S
LU inter
can be written as shown in equation (6).
n
uf
−
1
− log
2
n
uf
S
LU inter
=(
log
2
uf
+2)
×
(6)
Substituting equations (2) and (6) in equation (1), the expression of
S
LU
is
obtained as
S
LU
=
uf
−
1
n
log
2
uf
.
uf
×
(2
×
uf
−
log
2
uf
−
2)+(
log
2
uf
+2)
×
−
2.3 Derivation of
S
LUG
S
LUG
is dependent on intra-iteration switching (
S
LUG intra
) and inter-iteration
switching (
S
LUG inter
). So,
S
LUG
can be written as shown in equation (7).
S
LUG
=
S
LUG intra
+
S
LUG inter
(7)
S
LUG intra
is the total number of
0
0
bit transitions on the
address bus of the data memory, which takes place due to the memory address
references of the elements of array
a
, i.e.
a
[
i
]
,a
[
i
+1]
,a
[
i
+3]
,a
[
i
+2]
, ..., a
[
i
+
uf
−
to
−
1
and
1
−
to
−
2
+1]
,a
[
i
+
u
2
] (in (
uf
+1)
th
iteration, where, 0
≤ i<n
and
i
is a multiple of
uf
), within the body of the unrolled loop. For each iteration
ʲlsb
sof
b
follows
the Gray code sequence 0
,
1
,
3
,
2
,
,
u
2
+1
,
u
2
.So,
S
LUG intra
can be written
···
asshowninequation(8)
n
uf
×
S
LUG intra
=
(
uf
−
1)
(8)
where, (
uf
1) is the intra-iteration switching per iteration due to a Gray code
sequence of address references within the body of the unrolled loop.
S
LUG inter
is the total number of
0
−
0
bit transitions on the address
bus of the data memory, which takes place due to the last memory address
reference (of
a
[
i
curr
+
u
2
]) in the (
uf
+1)
th
iteration (current iteration), and
1
and
1
−
to
−
−
to
−
