Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence - VLSI Design and Test - page 87

The solution of the recurrence relation in equation (3) is shown in equation (4)

t ʲ =2 ʲ +1 − ʲ − 2 (4)

Substituting equation (4) in equation (2) S LU intra is obtained in equation (5)

n
uf ×

n
uf ×

(2 ʲ +1

S LU intra = − ʲ − 2) = (2 × uf − log 2 uf − 2) (5)

Let, i curr and i next be the values of i in the current and next iterations,

Inter-iteration bit transition for LU Inter-iteration bit transition for LUG

b a [ i curr + u 2 ] b a [ i next ]

Iteration i curr i next b a [ i curr + uf− 1] b a [ i next ]

Switching

Switching

1 0

16
32
48
64
80
96
112

16
32
48
64
80
96
112
128

0000 1111 0001 0000 5

6
5
7

0000 1000 0001 0000 2

2
3
4
5
6
7
8

0001 1111 0010 0000 0001 1000 0010 0000 3

2
4
2
3
2
5

0010 1111 0011 0000 0010 1000 0011 0000

0011 1111 0100 0000 0011 1000 0100 0000

0100 1111 0101 0000 5 0100 1000 0101 0000

0101 1111 0110 0000 6

5
8

0101 1000 0110 0000

0110 1111 0111 0000 0110 1000 0111 0000

0111 1111 1000 0000 0111 1000 1000 0000

Fig. 3. Inter-iteration switching on the address bus of data memory for first eight
iterations of LU and LUG in Fig. 2 (b) and (c), respectively, where, uf =16 and
base address ( a )=0

( Iteration ( ʷ ) ,Switching )

(1 ,ʲ +1)
(2 ,ʲ +2) , (3 ,ʲ +1)
(4 ,ʲ +3) , (5 ,ʲ +1) , (6 ,ʲ +2) , (7 ,ʲ +1)
(8 ,ʲ +4) , (9 ,ʲ +1) , (10 ,ʲ +2) , (11 ,ʲ +1) , (12 ,ʲ +3) , (13 ,ʲ +1) , (14 ,ʲ +2) , (15 ,ʲ +1)

···

(2 ʳ− 2 ,ʲ + ʳ − 2+1) , (2 ʳ− 2 +1 ,ʲ +1) ,···, (2 ʳ− 1 − 2 ,ʲ +2) , (2 ʳ− 1 − 1 ,ʲ +1)

(2 ʳ− 1 ,ʲ + ʳ − 1+1) , (2 ʳ− 1 +1 ,ʲ +1) ,···, (2 ʳ − 2 ,ʲ +2) , (2 ʳ

− 1 ,ʲ +1)

(a) Inter-iteration switching after each iteration from iteration 1 to iteration 2 ʳ − 1

Iteration Range
1
2 to 3
4 to 7
8 to 15

Total Switching
˃ 1 = ʲ +1
˃ 2 = ʲ +2+ ʲ +1=2 × ˃ 1 +1
˃ 3 = ʲ +3+ ʲ +1+ ʲ +2+ ʲ +1=2 × ˃ 2 +1
˃ 4 =2

=2 0 × ʲ +2 1

− 1

=2 1 × ʲ +2 2 − 1

=2 2 × ʲ +2 3 − 1

× ˃ 3 +1

=2 3

× ʲ +2 4 −

1

··· ··· ···

=2 ʳ− 2 × ʲ +2 ʳ− 1 ˃ ʳ− 1 =2 × ˃ ʳ− 2 +1

˃ ʳ =2 × ˃ ʳ− 1 +1

− 1 2 γ− 2 to 2 γ− 1 − 1

2 ʳ− 1 to 2 ʳ =2 ʳ− 1 × ʲ +2 ʳ − 1 − 1

(b) Total inter-iteration switching in mentioned iteration ranges

Fig. 4. Inter-iteration switching on the address bus of data memory for LU in Fig. 2(b),
where, base address ( a )=0