Baseband Hardware Designs in Modernised GNSS Receivers - Global Navigation Satellite Systems: Signal,Theory and Applications - page 40

which then demands a separate address generator. The read clock to the FIFO or the ROM is
nothing but the output of the code NCO.

Another issue with the memory codes is the way the codes are stored. The codes for all the
PRNs cannot be stored in a single memory because it will limit the access of the memory from
different channels. Hence the code for each PRN should be stored in a separate memory block.
Even in this situation, there is a constraint on the architecture. During the signal acquisition
or during the tracking if there is a requirement for more than one GNSS channel to use the
same PRN, then the memory block will have to have more than one port which is expensive
in terms of the resource and power consumption.

3.1.3 Effect on the accumulator bit-width

Another consequence of longer codes is that the number of bits in the accumulator has to
be increased, i.e. the N acc requirement increases (assuming that the accumulator is used to
integrate the correlation values for the duration of one code period).

3.2 Subcarrier modulation

3.2.1 Two-level (1-bit) subcarriers

With the subcarrier modulation an additional NCO, subcarrier generator and subcarrier
modulator may be required depending on the requirement of the tracking loops. If the
subcarrier has only two levels then the subcarrier and the replica code bit can be combined
with the help of a single XOR gate and the result will also be a 1-bit value. This does not
change the other parts of the correlation computation circuit and also the reference signal can
still be fed to the Add/Sub input of the accumulator.

3.2.2 Multi-level (> 1-bit) subcarriers

If the subcarrier has multiple levels (i.e. requiring more than 1-bit) then the process of
combining the replica code bit and the subcarrier is not a simple XOR operation, but requires a
negation operation which results in the same number of bits as the subcarrier ( N re f ) . Secondly,

the width of the shift register that generates the early, prompt and late values should be
increased to N re f . Since the reference signal is not represented by a single bit it cannot be used
directly as an input to the accumulator and therefore there needs to be a dedicated reference
signal mixer block. Thirdly, the reference signal mixing operation should accommodate this
bit-width increase in one of the inputs. As a result, the number of bits required to represent
the sample correlation value will increase, which in turn increases the number of bits in the
accumulator.

3.3 Modulation type

The BOC family of signals has a narrow autocorrelation main peak. As a result the spacing
between the R delayed versions of the reference signals should be reduced in order to achieve
better tracking performance (Shivaramaiah & Dempster, 2009). Reduction in the spacing
requires the code and the subcarrier NCO to be operating at a higher clock frequency. This
constrains the minimum clock frequency requirement of these NCOs. As a result, the overall