Baseband Hardware Designs in Modernised GNSS Receivers - Global Navigation Satellite Systems: Signal,Theory and Applications - page 39

x6 (E,P,L
and I,Q)

x6 (E,P,L
and I,Q)

x2 (I & Q)

Sample
Correlation

Accumulator Correlation

value IF Signal Logic /

LUT

Logic /
LUT

Clk

Add/Sub

(a)

x6 (E,P,L
and I,Q)

x2 (I & Q)

Sample
Correlation

IF Signal

Accumulator Correlation

value 2

16x4 LUT

4

Local Carrier

16

2

Clk

Add/Sub

Local Code

(b)

Fig. 3. Realisation of the correlation computation blocks (a) Generic implementation (b) an
implementation for the GPS L1 C/A signal

3.1 Longer codes (or longer code period)

3.1.1 Shift register generated codes

Longer codes are usually obtained by wide shift registers or a combination of shift registers.
Typically the baseband circuit will have the same number of code generators as the number of
channels. If the baseband has to implement multiple tracking channels to simultaneously
process multiple signals then the additional number of bits in the shift register brings in
additional hardware which is not insignificant.

3.1.2 Memory codes

Memory codes eliminate the need for a code generator (i.e the shift registers and XOR gates
used for the code generation). However the codes for all the pseudo random noise (PRN)
sequences must be stored in a circular buffer or ROM. The decision on whether to use a circular
buffer or ROM depends on the overall architecture of the receiver. For tracking the signal, it is
enough to read the buffer sequentially (like in a FIFO) and no address generation is required.
However if there is a requirement to read the local code from a particular delay (which could
be the case when the receiver wants to reacquire the signal) then it is better to use the ROM