Global Positioning System Reference
In-Depth Information
2.3.3 Carrier mixer (
N
1
)
The carrier mixer basically multiplies the input signal with the local carrier bits. Since the
resulting values will only have 8 levels
, a 3-bit encoding is sufficient.
Observe that with the 3-bit encoding, arithmetic operation cannot be directly performed.
Hence if the succeeding stage requires an arithmetic representation then four bits should be
used.
{±
1,
±
2,
±
3,
±
6
}
2.3.4 Subcarrier generator & subcarrier modulator (
N
re f
)
The local code takes on values of either 0 or 1 and hence 1-bit is sufficient for its representation.
However, the number of bits required to represent the subcarrier depends on the number of
levels in the subcarrier used for the modulation. BOC signals use a 2-level
{±
}
subcarrier
thus requiring only 1-bit for the representation. AltBOC uses 4-levels (dominant component
of the subcarrier) which require more bits for the representation and in such situations
approximation needs to be used to use smaller bit-width representations. The local spreading
code modifies only the sign of the subcarrier at the output of the subcarrier modulation.
Hence,
N
re f
will depend on the number of bits used for the subcarrier representation.
1
2.3.5 Local reference mixer (
N
2
)
This can be easily determined from the number of levels of the two inputs. However, the
succeeding stage (the accumulator) is an arithmetic operation and requires binary two's
complement representation. This leads to an additional bit at the output. For example, with
the 8-level
N
1
{±
1,
±
2,
±
3,
±
6
}
and the 4-level
N
re f
{±
1,
±
2
}
, the resultant set will have
only 12 levels
, but due to the later requirement of signed binary
representation the output must be 5-bit wide. Let the sample-maximum (magnitude) of the
output at this stage be denoted by
A
2
.
{±
1,
±
2,
±
3,
±
4,
±
6,
±
12
}
2.3.6 Accumulator (
N
acc
)
The interval between two consecutive accumulator resets is generally determined by the
coherent integration duration and the coherent integration duration in turn in most cases will
be a multiple of the spreading code period. Let
N
acc
denote the number of bits required to
represent the worst-case value at the output of the accumulator. Then
log
−
1
2
A
2
f
s
f
co
M
c
L
1
N
acc
=
+
C
+
(1)
R
+
is the sampling frequency in Hz,
R
+
is the chipping rate (with
∈
∈
where
f
s
f
co
any associated Doppler frequency) in Hz,
L
is
the number (or fraction) of primary code periods in the coherent integration and
C
is the
complex modulation indicator,
C
∈
N
is the primary code length,
M
c
∈
Q
∈{
=
=
}
. (1) clearly satisfies the
Design-For-Test (DFT) guidelines, but it is an overkill as all the samples may not end up with
a value of
A
2
. In reality the sample-maximum is controlled by the input signal strength and
the local carrier frequency. Hence the required accumulator width
N
acc
0
Normal
,1
Complex
N
acc
.
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