Reconfigurable Baseband Processing for Wireless Communications - Adaptive Signal Processing in Wireless Communications - page 459

is 6 µs [12], so the Montium HiperLAN/2 implementation can be considered a real-time
dynamically reconfigurable HiperLAN/2 system.
15.3.1.4.2 Frequency Scaling
Since the DSP kernels in the HiperLAN/2 receiver are mapped on different Montiums in
the SoC architecture, frequency scaling can easily be applied. Frequency scaling in com-
bination with voltage scaling is an important means to control the power consumption
of embedded systems. The idea of dynamic voltage scaling is to keep the supply voltage as
low as possible. The maximum operating frequency is tightly coupled to the supply voltage
level. This means that by downsca ling the clock frequency of hardware, the supply voltage
can be lowered as well, resulting in a quadratic decrease of the power consumption.
All DSP operations in the physical layer of the HiperLAN/2 communication system
are performed on OFDM symbols. Every OFDM symbol has a time period of 4 µs. So, it
should be ensured that every 4 µs a new OFDM symbol can be processed by the receiver.
Typically, the clock frequency of the NoC is fixed and the clock frequency of the tiles
can be varied. In case of block mode communication and under the assumption that the
clock frequency of the NoC is fixed at 100 MHz, the clock frequency of the Montium tile
for frequency offset correction has to be at least 25 MHz.
In case of block mode communication, the clock frequency of the NoC is equal to
the clock frequency of the reconfigurable processor tile and the clock frequency can be
adapted, and the clock frequency of the entire SoC (i.e., processor tiles and NoC) can
be scaled to its minimum value. The minimum clock frequency of the system would in
this case be reduced to 49 MHz for frequency offset correction. However, this situation
is fairly unlikely to happen because managing the adaptable clock frequency of the com-
mon NoC is rather complex.
Introducing the streaming communication mode variant of the DSP kernels in the
HiperLAN/2 receiver provides a situation where the data processing and input and out-
put communication are performed in parallel. In this case the data words are processed
immediately as they become available from the on-chip network, while previously pro-
cessed data are sent to the next stage of processing. Consequently, the communication
time is not a bottleneck. For example, the data processing for frequency offset correction
is performed during sixty-seven clock cycles, and because input and output are done
simultaneously, communication is reduced to sixty-four clock cycles. Processing needs
to complete in 4 µs. Hence, the minimum clock frequency of the Montium tile is 17 MHz
for frequency correction. In case of streaming communication, the clock frequency of
the NoC should be at least 17 MHz. Typically, the clock speed of the NoC is fixed to the
maximum operating frequency of the processing tiles.
15.3.1.5 Digital Broadcasting Systems
Many digital replacements of current analog broadcasting systems are available now-
adays. It is expected that within a few years all analog broadcasting services will be
switched off and replaced by digital standards like Digital Audio Broadcasting, Digital
Video Broadcasting, and Digital Radio Mondiale [14-16]. For example, in the United
States, television broadcasters have to switch from analog to digital before 2009. In the
Netherlands, almost 98% coverage of DVB-T has been achieved and analog television