Digital Signal Processing Reference
In-Depth Information
Table 15.7
Reconfigurable Hardware/Software Partitioning
of the HiperLAN/2 Functionality
Implemented
in
Multiplies per
MAC Frame
Additions per
MAC Frame
Determine frequency offset
Sotware
64
64
Determine equalizer coefficients
Sotware
0
0
Frequency offset correction
Montium
127,744
95,309
Inverse OFDM
Montium
383,232
574,848
Equalizer, phase offset, de-mapper
Montium
203,184
104,082
Table 15.8
Properties of the HiperLAN/2 Receiver Implementation
Frequency
Offset,
Correction
Equalizer,
Phase Offset,
De-Mapper
Inverse
OFDM
Execution time
[Cycles]
67
204
110
Block mode
Communication time
(input + output)
[Cycles]
128
116
<100
Minimum Montium + NoC clock
streaming communication
[MHz]
17
51
28
Minimum Montium + NoC clock
block communication
[MHz]
49
80
53
Minimum Montium clock with block
communication (NoC @ 100 MHz)
[MHz]
25
72
37
Configuration size
[Bytes]
274
946
576
Configuration time
[Cycles]
137
473
288
The table shows the impact of the communication overhead in the NoC, which can be
performed by streaming or block mode communication. Furthermore, the configura-
tion overhead of the DSP kernels implemented in the coarse-grained Montium is given.
15.3.1.4.1 Configuration
The configuration sizes of the Montium are small for the different functions (Table 15.8).
Montium tile 3 (see
Figure 15.11
)
, on which the inverse OFDM is performed, requires the
largest configuration. The configuration of tile 3 contains less than 1 kB of configuration
data. The configuration data are written into the configuration memory of the Montium
in 473 clock cycles, as every clock cycle 16 bits are written. So, tile 3 can be configured in
4.73 µs, which is dominating the time to switch from receive to transmit mode. Notice
that the maximum radio turnaround time* of the HiperLAN/2 communication system
* The radio turnaround time indicates the time to switch from transmit to receive mode in a com-
munication transceiver, and vice versa.
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