Reconfigurable Baseband Processing for Wireless Communications - Adaptive Signal Processing in Wireless Communications - page 440

The developments described above have their impact on wireless communications.
If the RAN is considered, (chip) area and power consumption are not of utmost impor-
tance. Engineering efficiency is important because RAN equipment is sold in relatively
low quantities. Flexibility is necessary in case new services have to be offered by the
RAN. Therefore, its functionality is implemented in GPPs and DSPs as much as pos-
sible. For example, in UMTS base stations, chip-level processing is done by means of
DSPs [54]. In UE, low power consumption has been the driving force, and large parts of
functionality are traditionally implemented in ASICs. However, nonrecurrent engineer-
ing costs and flexibility become more and more important. This has led to a trend where,
also in the UE, reconfigurable devices are becoming feasible.
In the remaining part of this chapter we will first discuss reconfigurable platforms
since they are attractive for both RAN and UE. Second, the implementation of wireless
communication applications on a reconfigurable platform will be described where we
separately deal with licensed communication and a form of unlicensed communica-
tion called cognitive radio. Third, we zoom into the process of mapping applications
onto a reconfigurable platform. Both the design time mapping and runtime mapping
are discussed.

15.2 Reconigurable Platforms

In [11], a definition of reconfigurable platforms is given: “Systems incorporating some
form of hardware programmability—customizing how the hardware is used using a
number of physical control points. These control points can then be changed periodi-
cally in order to execute different applications using the same hardware.” Based on this
definition, reconfigurable platforms can consist of fine-grained or coarse-grained func-
tional units [45]. Fine-grained functional units implement a function on a single bit
or a small number of bits, e.g., small lookup tables in a standard field programmable
gate array (FPGA). Coarse-grained functional units are typically much larger and may
consist of arithmetic and logic units (ALUs) and a significant amount of storage. Fine-
grained and coarse-grained reconfigurable devices are described separately.
For the wireless communications domain, conventional computing architectures
will be replaced by reconfigurable multiprocessor system-on-chips (MP-SoCs). On
MP-SoCs, several instances of a single type of processing device can be implemented.
These types of MP-SoCs are referred to as homogeneous tiled architectures. MP-SoCs
with several instances of a few different types of processing devices are referred to as
heterogeneous tiled architectures. We will give examples of both types of architectures.
To interconnect different processors on an MP-SoC, we use a NoC. NoCs are described
at the end of this section.

15.2.1 Fine-Grained Reconfigurable Devices
Recent advances in reconfigurable devices are based on the success of FPGAs. Within
an FPGA, static random access memory (SRAM) bits are connected to configuration
points. For example, writing to these SRAM bits, routing structures are configured and