Reconfigurable Baseband Processing for Wireless Communications - Adaptive Signal Processing in Wireless Communications - page 439

Table 15.1 Overview of Types of Processing
and Computing Devices

GPP DSP RP ASIC

GP processing * (*)

DS processing * * *

AS processing * * * *

Power efficiency - - - + ++

Area efficiency - - - + ++

Engineering efficiency ++ + - - -

Flexibility ++ + - - -

application-specific integrated circuits (ASICs). The ability to execute different types of
processing for the different types of computing devices is indicated in Table 15.1.
GPPs are able to execute all types of processing. DSPs are processors that are tai-
lored toward the signal processing domain. This is a relatively broad application domain,
and DSPs therefore resemble GPPs to a large extent; both GPPs and DSPs are typically
von Neumann machines [48]. Reconfigurable processors can be adapted in such a way
that different types of processing within a specific application domain can be executed.
ASICs generally are only suited for AS processing.
When mapping computing tasks onto computing devices, performance criteria of
computing devices are evaluated. Performance criteria are presented at the lower part
of Table 15.1. In general, the performance criteria are power, area, and engineering
efficiency and flexibility. Because ASICs basically have no control overhead, most dis-
sipated energy contributes to the execution of the tasks at hand. On the other hand,
since GPPs are based on the von Neumann principle, substantial energy is dissipated for
fetching and decoding instructions. From a power consumption perspective, this can
be considered as overhead leading to low power efficiency. DSPs are also based on the
von Neumann principle but are more power efficient. RPs show more ASIC-like behav-
ior and are therefore more power efficient than DSPs. Area efficiency relates to the area
required on an integrated circuit (IC) for realizing a specific task. ASICs are far more
area efficient than GPPs. Engineering efficiency refers to the relative engineering effort
required to have the computing device executing the demanded processing. For GPPs
and DSPs, in general, compilers are available to efficiently compile high-level sequential
code into machine instructions. Compilers for mapping applications onto RPs are not
yet as mature as for GPPs and DSPs. For ASICs, functionality can be specified by means
of schematic capture or a hardware specification language. However, the trajectory from
this specification to an integrated circuit is time-consuming, risky, and expensive. Flex-
ibility basically refers to the range of applications for which a computing device can be
used. It is clear the GPP offers the most flexibility and ASIC the least.
Because of the diminishing feature size of integrated circuits, more and more func-
tionality can be packed into a single chip. This has led to the creation of heterogeneous
system-on-chips (SoCs), where multiple processing cores of different types are intercon-
nected by means of a network-on-chip (NoC). An example can be found in [47].