Interfacing Standards - Computer Busses - page 87

MEMR Memory read (input/output). The memory read command indicates
a memory read when the memory address is in the range 100000h -
FFFFFFh (16 MB of memory).

MEMW Memory write (input/output). The memory write command indi-
cates a memory write when the memory address is in the range
100000h - FFFFFFh (16 MB of memory).

16-bit memory slave. Indicates that the addressed slave is a 16-bit
memory slave.

M16

16-bit I/O slave (input/output). Indicates that the addressed slave is
a 16-bit I/O slave.

IO16

DRQ0 , DRQ5-DRQ7

DMA request lines (input). Extra DMA request lines that indicate
that a slave device is requesting a DMA transfer.

DACK0 , DACK5-DACK7

DMA acknowledge lines (output). Extra DMA acknowledge lines
that indicate to the requesting slave that the DMA is handling its re-
quest.

Bus ready (input). This allows another processor to take control of
the system address, data and control lines.

MASTER

IRQ9-IRQ12 , IRQ14 , IRQ15 Interrupt requests (input). Additional interrupt request signals that
indicate that the slave device is requesting service by the processor.
Note that the IRQ13 line is normally used by the hard disk and in-
cluded in the IDE bus.

3.3.1 Handshaking lines
Figure 3.5 shows a typical connection to the ISA bus. The ALE (or sometimes known as
BALE) controls the address latch and, when active low, it latches the address lines A2-A19
to the ISA bus. The address is latched when ALE goes from a high to a low.
The Pentium's data bus is 64 bits wide, whereas the ISA expansion bus is 16-bits wide. It
is the bus controller's function to steer data between the processor and the slave devic e f or
eith er 8- bi t or 1 6-bit com munications. For this purpose the bus controller monitors BE0 -
BE3 , /W , M16 and IO16 to determine the movement of data.

When the p roc essor outputs a valid address it sets address lines (AD2-AD31), the byte
enables ( BE0 - BE3 ) and sets ADS active. The bus controller then picks up this address and
uses it to generate the system address lines, SA0-SA19 (which are just a copy of the lines
A2-A19. The bus controller then uses the byte enable lines to generate the address bits SA0
and SA1.
The EADS signal returns an active low signal to the processor if the external bus control-
ler has sent a valid address on address pins A2-A21.
It can be seen from Figure 3.6 that the BE0 line accesses the addresses ending with 0h,
4h, 8h and Ch, the BE1 line accesses addresses ending with 1h, 5h, 9h and Dh, the BE2 line
accesses addresses ending with 02, 5h, Ah and Eh, and so on.
Thus if the BE0 line is asserted and the SBHE line is high then a single byte is accessed
through the D0-D7. If a word is to be accessed then SBHE is low and D0-D15 contains the
data.

R