Information Technology Reference
In-Depth Information
D0-D31
D0-D15
Data
latch
Memory
Processor
Address
latch
A2-A31
A2-A19
ISA
bus
BE0-BE3
ALE
A0
A1
SBHE
M16
IO16
Bus
controller
EADS
Figure 3.5
ISA bus connections
000Ah
BE2
0009h
BE1
0008h
BE0
C
D
E
F
0007h
BE3
0006h
BE2
8
9
A
B
0005h
BE1
0004h
4
5
6
7
BE0
0003h
BE3
0
1
2
3
0002h
BE2
0001h
BE1
BE0
BE1
BE2
BE3
D0-D7
D8-D15
D16-D23
D24-D31
0000h
BE0
Figure 3.6
Address decoding
Table 3.1 shows three examples of handshaking lines. The first is an example of a byte trans-
fer with an 8-bit slave at an even address. The second example gives a byte transfer for an 8-
bit slave at an odd address. Finally, the table shows a 2-byte transfer with a 16-bit slave at an
even address.
Table 3.1
Example handshaking lines
BE0
BE1
BE2
BE3
IO16
M16
SBHE
SA0
SA1
Data
0
1
1
1
1
1
1
0
0
SD0-SD7
1
0
1
1
1
1
0
1
0
SD8-SD15
0
0
1
1
0
1
0
0
0
SD0-SD15
If 32-bit data is to be accessed then BE0-BE3 will each be 0000 which makes 4 bytes active.
The bus controller will then cycle through SA0, SA1 = 00 to SA0, SA1 = 11. Each time the
8-bit data is placed into a copy buffer which is then passed to the processor as 32 bits.
