Information Technology Reference
In-Depth Information
the 486 processor).
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Branch prediction with an on-chip branch table which improves looping characteristics.
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Enhancement to the virtual-8086 mode to allow for 4 MB as well as 4 KB pages.
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128-bit and 256-bit data paths are possible (although the main registers are still 32 bits).
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Burstable 64-bit external data bus.
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Addition of advanced programmable interrupt controller (APIC) to support multiple Pen-
tium processors.
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New dual processing mode to support dual processor systems.
The Pentium processor has been extremely successful and has helped support enhanced mul-
titasking operating systems such as Microsoft Windows. The Intel Pentium Pro enhanced the
Pentium processor with the following:
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Incorporation of a three-way superscalar architecture, as apposed to a 2-way for the Pen-
tium. This allows three instructions to be executed for every clock cycle.
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Uses enhanced prediction of parallel code (called dynamic execution microarchitecture)
for the superscalar operation. This includes methods such as microdata flow analysis, out-
of-order execution, enhanced branch prediction and speculative execution. The three in-
struction decode units work in parallel to decode object code into smaller operations
called micro-ops. These micro-ops then go into an instruction pool, and, when there are
no interdependencies they can be executed out-of-order by the five parallel execution
units (two integer units, two for floating-point operations and one for memory opera-
tions). A retirement unit retires completed micro-ops in their original program order, tak-
ing account of any branches. This recovers the original program flow.
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Addition of register renaming. Multiple instructions not dependent on each other, using
the same registers, allow the source and destination registers to be temporarily renamed.
The original register names are used when instructions are retired and program flow is
maintained.
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Addition of a, closely coupled, on-package, 256 KB L2 cache which has a dedicated 64-
bit full clock speed bus. The L2 cache also supports up to four concurrent accesses
through a 64-bit external data bus. Each of these accesses is transaction-oriented where
each access is handled as a separate request and response. This allows for numerous re-
quests while awaiting a response.
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Expanded 36-bit address bus to give a physical address size of 64 GB.
The Pentium II/III processor is a further enhancement to the processor range. Apart from
increasing the clock speed it has several enhancements over the Pentium Pro, including:
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Integration of MMX technology. MMX instructions support high-speed multimedia op-
erations and include the addition of eight new registers (MM0 to MM7), four MMX data
types and an MMX instruction set.
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Single edge contact (SEC) cartridge packaging. This gives improved handling perform-
ance and socketability. It uses surface mount components and has a thermal plate (which
accepts a standard heat sink), a cover and a substrate with an edge finger connection.
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Integrated on-chip L1 cache 16 KB for code and another 16 KB for data. This has since
been increased to 512 KB cache.
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Increased size, on-package, 512 KB L2 cache.
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Enhanced low-power states, such as AutoHALT, Stop-Grant, Sleep and Deep Sleep.
