Information Technology Reference
In-Depth Information
Table A.3
Processor comparison
Processor
Clock
(when
released)
Register
size
External
data bus
Maxi-
mum
external
memory
Cache
Perform-
ance
(MIPs)
8086
8 MHz
16
16
1 MB
0.8
286
12.5 MHz
16
16
16 MB
2.7
386DX
20 MHz
32
32
4 GB
6.0
486DX
25 MHz
32
32
4 GB
8KB L1
20
Pentium
60 MHz
32
64
4 GB
16KB L1
100
Pentium Pro
200 MHz
32
64
64 GB
16KB L1
256KB L2
440
Pentium II/III
300 MHz
32
64
64 GB
16KB L1
512KB L2
700
A.4.1 Intel processor development
The 80386 processor was a great leap in processing power over the 8086 and 80286, but it
required an on-board maths co-processor to be added to enhance its mathematical operations.
It could also only execute one instruction at a time. The 486 brought many enhancements,
such as:
•
The addition of parallel execution with the expansion of the instruction decode and exe-
cution units into five pipelined stages. Each of these stages operate in parallel with the
others on up to five instructions in different stages of execution. This allows up to five in-
structions to be completed at a time.
•
The addition of an 8 KB on-chip cache to greatly reduce the time taken to access data and
code.
•
The addition of an integrated floating-point unit.
•
Support for more complex and powerful systems, such as off-board L2 cache support and
multiprocessor operation.
With the increase in notebook and palmtop computers, the 486 was also enhanced to support
many energy and system management capabilities. These processors were named the 486SL
processors. The new enhancements included:
•
System management mode - this mode is triggered by the processor's own interrupt pin
and allows complex system management features to be added to a system transparently to
the operating system and application programs.
•
Stop clock and auto halt powerdown - these allow the processor to either shut itself down
(and preserve its current state) or run at a reduced clock rate.
The Intel Pentium processor added many enhancements to the previous processors, includ-
ing:
•
The addition of a second execution pipeline. These two pipelines, named u and v, can
execute two instructions per clock. This is known as superscalar operation.
•
Increased on-chip L1 cache 8 KB for code and another 8 KB for data. It uses the MESI
protocol to support write-back mode, as well as the write-through mode (which is used by
