PC Processors - Computer Busses - page 494

tem clock speed and are referred to as DX4 processors. These include the Intel DX4-100 (25
MHz clock) and Intel DX4-75 (25 MHz clock).
The Pentium (or P-5) is a 64-bit 'superscalar' processor. It can execute more than one
instruction at a time and has a full 64-bit (8-byte) data bus and a 32-bit address bus. In terms
of performance, it operates almost twice as fast as the equivalent 80486. It also has improved
floating-point operations (roughly three times faster) and is fully compatible with previous
80x86 processors.
The Pentium II/III is an enhancement of the P-5 and has a bus which supports up to four
processors on the same bus without extra supporting logic. With clock multiplying speeds of
over 500 MHz are possible. It also has major savings of electrical power and the minimisa-
tion of electromagnetic interference (EMI). A great enhancement of the Pentium II/III bus is
that it detects and corrects all single bit data bus errors and also detects multiple bit errors on
the data bus.

A.2 8086/88

A.2.1 Introduction
The great revolution in processing power arrived with the 16-bit 8086 processor. This had a
20-bit address bus and a 16-bit address bus, whereas the 8088 has an 8-bit external data bus.
Figure A.1 shows the pin connections of the 8086 and also the main connections to the proc-
essor. Many of the 40 pins of the 8086 have dual functions. The lines AD0-AD7 act either a
the lower eight bits of the address bus (A0-A7) or as the lower eight bits of the data bus
(D0-D7). The lines A16/S3-A19/S6 also have a dual function, S3-S6 are normally not used
by the PC thus they are used as the four upper bits of the address bus. The latching of the
address is achieved when the ALE (address latch enable) goes from a high to a low.
Th e bus c ontroller (8288) g en erates the re quired contr ol signals form the 8088 s tatus
lines S0 - S2 . For example, if S0 is high, S1 is low and S2 is low then the MEMR line
goes low. The main control signals are:

• IOR (I/O read) which means that the processor is reading from the contents of the address

which is on the I/O bus.

• IOW (I/O write) which means that the processor is writing the contents of the data bus to

t he add ress which is on the I/O bus.

• MEMR (memory read) which means that the processor is reading from the contents of

the address which is on the address bus.

• MEMW (memory write) which means that the processor is writing the contents of the

data b us to the address which is on the address bus.

• INTA (inte rru pt a ckno wl edgement) which is used by the processor to acknowledge an

interrupt ( S0 , S1 and S2 all go low). When a peripheral wants the attention of the proc-
essor it sends an interrupt request to the 8259 which, if it is allowed, sets the INTR high.

The processor either communicates directly with memory (with MEM W and MEMR ) or
communicates with peripherals through isolated I/O ports (with IOR and IOW ).