AGP - Computer Busses - page 197

The 440LX is the first AGPset product designed to support the AGP interface. The HOST
BRIDGE AGP implementation is compatible with the accelerated graphics port Specification
1.0. HOST BRIDGE supports only a synchronous AGP interface, coupling to the host bus
frequency. The AGP interface can reach a theoretical ~532 Mbytes/sec transfer rate. The
actual bandwidth will be limited by the capability of the HOST BRIDGE memory subsys-
tem.
11.1.1 PCI interface
The HOST BRIDGE PCI interface is 33-MHz Revision 2.1 compliant and supports up to
five external PCI bus masters in addition to the I/O bridge (PIIX4). HOST BRIDGE supports
only synchronous PCI coupling to the host bus frequency.
HOST BRIDGE defines a sophisticated data buffering scheme to support the required
level of concurrent operations and provide adequate sustained bandwidth between the
DRAM subsystem and all other system interfaces (CPU, AGP and PCI).
11.2 PCI and AGP
AGP defines the master as the graphics controller and the corelogic as the graphics card. The
AGP interface is based on the 66 MHz PCI standard, but has four additional exten-
sions/enhancements. These extensions are:
• Deeply pipelined memory read and write operations, which fully hide memory access
latency.
• Address bus and data bus demultiplexing, allowing for nearly 100% bus efficiency.
• Extension to the PCI timing cycle which allows for one or two data transfers per 66 MHz
clock cycle. This provides a maximum data rate of 500 MB/s.
• Extension to the PCI timing cycle which allows for four data transfers per 66 MHz clock
cycle. This provides for a maximum data rate of 1 GB/s.
All these enhancements are implemented using extra signal lines (sideband signals), and it is
not intended as a replacement to the PCI bus. The AGP is physically, logically and electri-
cally independent of the PCI bus, and has its own connector which is reserved solely for
graphics devices (and is not interchangeable with the AGP connector). Figure 11.2 shows the
main AGP signal lines.
AGP uses deep pipelining which allows the total memory READ throughput equal to that
which is possible for memory WRITE (in PCI the memory read throughput is about half of
memory write throughput, as memory read access time is visible as wait states on this un-
pipelined bus). This and optional higher transfer rates and address demultiplexing, allows for
a large increase in memory read throughput over standard PCI implementations.