Information Technology Reference
In-Depth Information
PIPE
PIPE
AGP
addressing
AGP
addressing
SBA[7:0]
SBA[7:0]
GFRAME
GIRDY
GTRDY
GSTOP
GD
EVSEL
GPERR
GSERR
GREQ
GGNT
0]
GFRAME
GFRAME
GIRDY
GIRDY
GTRDY
RBF
RBF
AGP
flow
control
AGP
flow
control
GTRDY
GSTOP
GSTOP
GDEVSEL
WBF
WBF
GDEVSEL
GPERR
PCI
signals
PCI
signals
AGP
AGP
connector
AGP
AGP
connector
AGP
status
AGP
status
AGP
connector
AGP
connector
GPERR
GSERR
ST[2:0]
ST[2:0]
GSERR
GREQ
GREQ
GGNT
AD_STB0
AD_STB0
AD_STB0 /AD_STB0
/AD_STB0
/AD_STB0
GGNT
0]
AD_STB1
AD_STB1
AD_STB1 /AD_STB1
/AD_STB1
/AD_STB1
GAD[15
GAD[15
GAD[15
:
:
:
0]
AGP
clocks/
strobe
AGP
clocks/
strobe
GC/BE[3
GC/B
E[3
GPAR
GC/BE[3
GPAR
:
:
:
0]
0]
0]
SB_STB1 /SB_STB1
SB_STB1
CLK
SB_STB1
CLK
/SB_STB1
/SB_STB1
GPAR
Figure 11.2
The main AGP signal lines
11.3 Bus transactions
AGP uses two types of bus operation. These are:
•
Queuing requests
. This can be done over the SBA port, or the AD bus, and is set up
using Bit 9 for the status register (only one type at a time can be used). With the SBA
port, the AD bus cannot be used, and vice versa. The sideband signals (SBA[7:0]) are
used exclusively to transmit AGP access requests (all PCI transactions use the AD pins
for both data and address), and are sent from the master to the core logic (the AGP re-
quests are the same when sent
over t
he AD bus or the SBA bus). A master that uses the
SBA port does not require the
PIPE
signal which is used only to frame requests on the
AD pins.
•
Address demultiplexing option
. This allows the complete AGP access request to be
transmitted over the 8-bit SBA port. For this the request is broken into three parts: low-
order address bits and length (type 1), mid-order address bits and command (type 2), and
high-order address bits (type 3).
11.4 Pin description
AGP adds an extra 21 signal lines to the PCI specification. The basic implementation of
AGP should support ×1 and ×2 transfer rates, and may optionally support ×4 data transfer
rates. All devices should support low priority (LP) data writes, but optionally support fast
write (FW) data transfers.
.
